ZHCS603D November 2011 – April 2022 SN65HVDA100-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | |
|---|---|---|---|---|---|---|
| VSUP SUPPLY | ||||||
| VSUP | Operational supply voltage (ISO 17987-4 Param 10)(2) | 5 | 14 | 27 | V | |
| VSUP | Nominal supply voltage (ISO 17987-4 Param 10) | Normal and standby modes | 7 | 14 | 18 | V |
| Sleep mode | 7 | 12 | 18 | |||
| UVSUP | Undervoltage VSUP threshold | 4.35 | 4.65 | V | ||
| UVHYS | Delta hysteresis voltage for VSUP undervoltage threshold | 0.2 | V | |||
| ISUP | Supply current | Normal mode, EN = high, Bus dominant (total bus load where RLIN ≥ 500 ? and CLIN ≤ 10 nF (see Figure 8-1 )(3), INH = VSUP, NWake = VSUP | 1.2 | 7.5 | mA | |
| Standby mode, EN = low, Bus dominant (total bus load where RLIN ≥ 500 ? and CLIN ≤ 10 nF (see Figure 8-1)(3), INH = VSUP, NWake = VSUP | 1 | 2.1 | mA | |||
| Normal mode, EN = high, Bus recessive, LIN = VSUP, INH = VSUP, NWake = VSUP | 450 | 775 | μA | |||
| Standby mode, EN = low, Bus recessive, LIN = VSUP, INH = VSUP, NWake = VSUP | 450 | 775 | μA | |||
| Sleep mode, 7 V < VSUP ≤ 14 V, LIN = VSUP, NWake = VSUP, EN = 0 V, TXD and RXD floating | 10 | 20 | μA | |||
| Sleep mode, 14 V < VSUP < 27 V, LIN = VSUP, NWake = VSUP, EN = 0 V, TXD and RXD floating | 30 | μA | ||||
| RXD OUTPUT PIN (OPEN DRAIN) | ||||||
| VO | Output voltage(4) | –0.3 | 5.5 | V | ||
| IOL | Low-level output current, open drain | LIN = 0 V, RXD = 0.4 V | 3.5 | mA | ||
| IIKG | Leakage current, high-level | LIN = VSUP, RXD = 5 V | –5 | 0 | 5 | μA |
| TXD INPUT/OUTPUT PIN | ||||||
| VIL | Low-level input voltage | –0.3 | 0.8 | V | ||
| VIH | High-level input voltage | 2 | 5.5 | V | ||
| VIT | Input threshold hysteresis voltage | 30 | 500 | mV | ||
| Pulldown resistor | 125 | 350 | 800 | k? | ||
| IIL | Low-level input leakage current | TXD = Low | –5 | 0 | 5 | μA |
| ITXD_Wake | Local wake up source re recognition TXD open drain drive | Standby mode after a local wake up event, VLIN = VSUP, NWake = 0 V, TXD = 1 V | 1.3 | 4.6 | 8 | mA |
| LIN PIN (REFERENCED TO VSUP) | ||||||
| VOH | High-level output voltage | LIN recessive, TXD = high, IO = 0 mA, VSUP = 14 V | VSUP – 1 | V | ||
| VOL | Low-level output voltage | LIN dominant, TXD = low, IO = 40 mA, VSUP = 14 V | 0.2 × VSUP | V | ||
| IL | Limiting current (ISO 17987-4 Param 12) | TXD = 0 V, VLIN = 7 V to 27 V | 40 | 90 | 200 | mA |
| ILKG | Receiver leakage current, dominant (ISO 17987-4 Param 13) | LIN = 0 V, 7 V ≤VSUP ≤ 18 V, Driver off | –1 | mA | ||
| Receiver leakage current, recessive (ISO 17987-4 Param 14) | LIN ≥ VSUP, 7 ≤ VSUP ≤18 V, Driver off | 20 | μA | |||
| LIN = VSUP, driver off | –5 | 5 | ||||
| ILKG | Leakage current, loss of ground (ISO 17987-4 Param 15) | GND = VSUP , VSUP = 12 V, 0 V < VLIN < 18 V | –1 | 1 | mA | |
| ILKG | Leakage current, loss of supply (ISO 17987-4 Param 16) | 7 V < LIN ≤ 12 V, VSUP = GND | 5 | μA | ||
| 12 V < LIN ≤ 18 V, VSUP = GND | 10 | |||||
| VIL | Low-level input voltage (ISO 17987-4 Param 17) | LIN dominant (including LIN dominant for wake up) | 0.4 × VSUP | V | ||
| VIH | High-level input voltage (ISO 17987-4 Param 18) | LIN recessive | 0.6 × VSUP | V | ||
| VBUS_CNT | Receiver center threshold (ISO 17987-4 Param 19) | VBUS_CNT = (VIL + VIH) / 2 | 0.475 x VSUP | 0.5 × VSUP | 0.525 x VSUP | V |
| VHYS | Hysteresis voltage (ISO 17987-4 Param 20) | VHYS = (VIL - VIH) | 0.05 × VSUP | 0.175 × VSUP | V | |
| VSERIAL_ DIODE | Serial diode in LIN termination pull up path (ISO 17987-4 Param 21) | By design and characterization | 0.4 | 0.7 | 1.0 | V |
| RRESPONDER | Pullup resistor to VSUP (ISO 17987-4 Param 26) | Normal and standby modes | 20 | 30 | 60 | k? |
| RSLEEP | Pullup current source to VSUP | Sleep mode, VSUP = 14 V, LIN = GND | –2 | –20 | μA | |
| EN INPUT PIN | ||||||
| VIL | Low-level input voltage | –0.3 | 0.8 | V | ||
| VIH | High-level input voltage | 2 | 5.5 | V | ||
| Vhys | Hysteresis voltage | By design and characterization | 30 | 500 | mV | |
| Pulldown resistor | 125 | 350 | 800 | k? | ||
| IIL | Low-level input current | EN = Low | –5 | 0 | 5 | μA |
| INH OUTPUT PIN | ||||||
| RDS(on) | ON-state resistance | Between VSUP and INH, INH = 2-mA drive, Normal or standby mode | 25 | 50 | ? | |
| IIKG | Leakage current | Low-power mode, 0 < INH < VSUP | –5 | 0 | 5 | μA |
| NWAKE INPUT PIN | ||||||
| VIL | Low-level input voltage | –0.3 | VSUP – 3.3 | V | ||
| VIH | High-level input voltage | VSUP – 1 | VSUP + 0.3 | V | ||
| Pullup current | NWake = 0 V | –45 | –10 | –2 | μA | |
| IIKG | Leakage current | VSUP = NWake | –5 | 0 | 5 | μA |
| AC CHARACTERISTICS | ||||||
| D1 | Duty cycle 1(5) (ISO 17987-4 Param 27) | THREC(max) = 0.744 × VSUP, THDOM(maximum) = 0.581 × VSUP, VSUP = 7 V to 18 V, tBIT = 50 μs (20 kbps), D1 = tBus_rec(min)/ (2 × tBIT) (see Figure 7-1) | 0.396 | |||
| D2 | Duty cycle 2(5) (ISO 17987-4 Param 28) | THREC(min) = 0.422 × VSUP, THDOM(min) = 0.284 × VSUP, VSUP = 7.6 V to 18 V, tBIT = 50 μs (20 kbps), D2 = tBus_rec(max)/ (2 × tBIT) (see Figure 7-1) | 0.581 | |||
| D3 | Duty cycle 3(5) (ISO 17987-4 Param 29) | THREC(max) = 0.778 × VSUP, THDOM(max) = 0.616 × VSUP, VSUP = 7 V to 18 V, tBIT = 96 μs (10.4 kbps), D3 = tBus_rec(min)/ (2 × tBIT) (see Figure 7-1) | 0.417 | |||
| D4 | Duty cycle 4(5) (ISO 17987-4 Param 30) | THREC(min) = 0.389 × VSUP, THDOM(min) = 0.251 × VSUP, VSUP = 7.6 V to 18 V, tBIT = 96 μs (10.4 kbps), D4 = tBus_rec(max)/ (2 × tBIT) (see Figure 7-1) | 0.59 | |||