ZHCSIM2D June 2010 – August 2021 PCM9211
PRODUCTION DATA
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MPC3FLG3 | MPC3FLG2 | MPC3FLG1 | MPC3FLG0 | MPC2FLG3 | MPC2FLG2 | MPC2FLG1 | MPC2FLG0 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
| MPC3FLG[3:0]: MPIO_C3 Pin, Flag Select | ||
| 0000: | CLKST (default) | |
| 0001: | EMPH | |
| 0010: | BPSYNC | |
| 0011: | DTSCD | |
| 0100: | PARITY | |
| 0101: | LOCK | |
| 0110: | VOUT | |
| 0111: | UOUT | |
| 1000: | COUT | |
| 1001: | BFRAME | |
| 1010: | FSOUT0 | |
| 1011: | FSOUT1 | |
| 1100: | FSOUT2 | |
| 1101: | FSOUT3 | |
| 1110: | INT0 | |
| 1111: | INT1 | |
| MPC2FLG[3:0]: MPIO_C2 Pin, Flag Select | ||
| 0000: | CLKST (default) | |
| 0001: | EMPH | |
| 0010: | BPSYNC | |
| 0011: | DTSCD | |
| 0100: | PARITY | |
| 0101: | LOCK | |
| 0110: | VOUT | |
| 0111: | UOUT | |
| 1000: | COUT | |
| 1001: | BFRAME | |
| 1010: | FSOUT0 | |
| 1011: | FSOUT1 | |
| 1100: | FSOUT2 | |
| 1101: | FSOUT3 | |
| 1110: | INT0 | |
| 1111: | INT1 | |
These register settings are effective only at MPCSEL[2:0] = 011, MPC3SEL = 0, and MPC2SEL = 0.