ZHCSIM2D June 2010 – August 2021 PCM9211
PRODUCTION DATA
| PIN | I/O | 5-V TOLERANT | DESCRIPTION | |
|---|---|---|---|---|
| NO. | NAME | |||
| 1 | ERROR/INT0 | O | No | DIR error detection output / interrupt 0 output |
| 2 | NPCM/INT1 | O | No | DIR non-PCM detection output / interrupt 1 output |
| 3 | MPIO_A0 | I/O | Yes | Multipurpose I/O, group A(1) |
| 4 | MPIO_A1 | I/O | Yes | Multipurpose I/O, group A(1) |
| 5 | MPIO_A2 | I/O | Yes | Multipurpose I/O, group A(1) |
| 6 | MPIO_A3 | I/O | Yes | Multipurpose I/O, group A(1) |
| 7 | MPIO_C0 | I/O | Yes | Multipurpose I/O, group C(1) |
| 8 | MPIO_C1 | I/O | Yes | Multipurpose I/O, group C(1) |
| 9 | MPIO_C2 | I/O | Yes | Multipurpose I/O, group C(1) |
| 10 | MPIO_C3 | I/O | Yes | Multipurpose I/O, group C(1) |
| 11 | MPIO_B0 | I/O | Yes | Multipurpose I/O, group B(1) |
| 12 | MPIO_B1 | I/O | Yes | Multipurpose I/O, group B(1) |
| 13 | MPIO_B2 | I/O | Yes | Multipurpose I/O, group B(1) |
| 14 | MPIO_B3 | I/O | Yes | Multipurpose I/O, group B(1) |
| 15 | MPO0 | O | No | Multipurpose output 0 |
| 16 | MPO1 | O | No | Multipurpose output 1 |
| 17 | DOUT | O | No | Main output port, serial digital audio data output |
| 18 | LRCK | O | No | Main output port, LR clock output |
| 19 | BCK | O | No | Main output port, bit clock output |
| 20 | SCKO | O | No | Main output port, system clock output |
| 21 | DGND | – | – | Ground, for digital |
| 22 | DVDD | – | – | Power supply, 3.3 V (typ), for digital |
| 23 | MDO/ADR0 | I/O | Yes | Software control I/F, SPI data output / I2C slave address setting 0(1) |
| 24 | MDI/SDA | I/O | Yes | Software control I/F, SPI data input / I2C data input/output(1)(4) |
| 25 | MC/SCL | I | Yes | Software control I/F, SPI clock input / I2C clock input(1) |
| 26 | MS/ADR1 | I | Yes | Software control I/F, SPI chip select / I2C slave address setting 1(1) |
| 27 | MODE | I | No | Control mode setting, (see the Section 7.4.2 section, control mode pin setting) |
| 28 | RXIN7/ADIN0 | I | Yes | Biphase signal, input 7 / AUXIN0, serial audio data input(1) |
| 29 | RXIN6/ALRCKI0 | I | Yes | Biphase signal, input 6 / AUXIN0, LR clock input(1) |
| 30 | RXIN5/ABCKI0 | I | Yes | Biphase signal, input 5 / AUXIN0, bit clock input(1) |
| 31 | RXIN4/ASCKI0 | I | Yes | Biphase signal, input 4 / AUXIN0, system clock input(1) |
| 32 | RXIN3 | I | Yes | Biphase signal, input 3(1) |
| 33 | RXIN2 | I | Yes | Biphase signal, input 2(1) |
| 34 | RST | I | Yes | Reset input, active low(1)(2) |
| 35 | RXIN1 | I | Yes | Biphase signal, input 1, built-in coaxial amplifier |
| 36 | VDDRX | – | – | Power supply, 3.3 V (typ.), for RXIN0 and RXIN1. |
| 37 | RXIN0 | I | Yes | Biphase signal, input 0, built-in coaxial amplifier |
| 38 | GNDRX | - | - | Ground, for RXIN |
| 39 | XTI | I | No | Oscillation circuit input for crystal resonator or external XTI clock source input(3) |
| 40 | XTO | O | No | Oscillation circuit output for crystal resonator |
| 41 | AGND | – | – | Ground, for PLL analog |
| 42 | VCC | – | – | Power supply, 3.3 V (typ), for PLL analog |
| 43 | FILT | O | No | External PLL loop filter connection terminal; must connect recommended filter |
| 44 | VCOM | O | No | ADC common voltage output; must connect external decoupling capacitor |
| 45 | AGNDAD | – | – | Ground, for ADC analog |
| 46 | VCCAD | – | – | Power supply, 5.0 V (typ), for ADC analog |
| 47 | VINL | I | No | ADC analog voltage input, left channel |
| 48 | VINR | I | No | ADC analog voltage input, right channel |