ZHCSIM2D June 2010 – August 2021 PCM9211
PRODUCTION DATA
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSV | TXSSRC2 | TXSSRC1 | TXSSRC0 | RSV | TXPSRC2 | TXPSRC1 | TXPSRC0 |
| R/W-0h | R/W-1h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-0h |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
| TXSSRC[2:0]: DIT System Clock Source Select | ||
| 000: | DIR/ADC Automatic (DIR lock = DIR, DIR unlock = ADC) | |
| 001: | DIR | |
| 010: | ADC | |
| 011: | AUXIN0 | |
| 100: | AUXIN1 (default) | |
| 101: | AUXIN2 | |
| 110: | Reserved | |
| 111: | Reserved | |
| TXPSRC[2:0]: DIT Bit Clock, LR Clock, Data Source Select | ||
| 000: | DIR/ADC Automatic (DIR lock = DIR, DIR unlock = ADC) | |
| 001: | DIR | |
| 010: | ADC | |
| 011: | AUXIN0 | |
| 100: | AUXIN1 (default) | |
| 101: | AUXIN2 | |
| 110: | Reserved | |
| 111: | Reserved | |