ZHCSAC2C August 2012 – October 2018 PCM5121 , PCM5122
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Terminology
- 8.3.2 Audio Data Interface
- 8.3.3 XSMT Pin (Soft Mute / Soft Un-Mute)
- 8.3.4 Audio Processing
- 8.3.5 DAC Outputs
- 8.3.6
Reset and System Clock Functions
- 8.3.6.1 Clocking Overview
- 8.3.6.2 Clock Slave Mode With Master and System Clock (SCK) Input (4 Wire I2S)
- 8.3.6.3 Clock Slave Mode With BCK PLL to Generate Internal Clocks (3-Wire PCM)
- 8.3.6.4 Clock Generation Using the PLL
- 8.3.6.5 PLL Calculation
- 8.3.6.6 Clock Master Mode from Audio Rate Master Clock
- 8.3.6.7 Clock Master from a Non-Audio Rate Master Clock
- 8.4 Device Functional Modes
- 8.5 Programming
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Register Maps
- 13器件和文檔支持
- 14機械、封裝和可訂購信息
8.3.6.7 Clock Master from a Non-Audio Rate Master Clock
The classic example here is running a 12-MHz Master clock for a 48-kHz sampling system. Given the clock tree for the device (shown in Figure 63), a non-audio clock rate cannot be brought into the SCK to the PLL in master mode. Therefore, the PLL source must be configured to be a GPIO pin, and the output brought back into another GPIO pin.
Figure 65. Application Diagram for Using Non-Audio Clock Sources to Generate Audio Clocks The clock flow through the system is shown in Figure 65. The newly-generated SCK must be brought out of the device on a GPIO pin, then brought into the SCK pin for integer division to create BCK and LRCK outputs.
NOTE
Pullup resistors must be used on BCK and LRCK in this mode to ensure the device does not go into sleep mode.
A code example for configuring this mode is provided in the PCM5242 data sheet (SLASE12).