ZHCSAC2C August 2012 – October 2018 PCM5121 , PCM5122
PRODUCTION DATA.
The system clock PLL mode allows designers to use a simple 3-wire I2S audio source. The 3-wire source reduces the need for a high frequency SCK, making PCB layout easier, and reduces high frequency electromagnetic interference.
In hardwired mode, the internal PLL is disabled as soon as an external SCK is supplied.
In hardwired mode, the device starts up expecting an external SCK input, but if BCK and LRCK start correctly while SCK remains at ground level for 16 successive LRCK periods, then the internal PLL starts, automatically generating an internal SCK from the BCK reference. Specific BCK rates are required to generate an appropriate master clock.Table 33 describes the minimum and maximum BCK per LRCK for the integrated PLL to automatically generate an internal SCK.
In software mode, the user must set all the PLL registers and clock divider registers for referencing BCK. See the Clock Generation Using the PLL section for more information.
| SAMPLE F (kHz) | BCK (fS) | |
|---|---|---|
| 32 | 64 | |
| 8 | – | – |
| 16 | – | 1.024 |
| 32 | 1.024 | 2.048 |
| 44.1 | 1.4112 | 2.8224 |
| 48 | 1.536 | 3.072 |
| 96 | 3.072 | 6.144 |
| 192 | 6.144 | 12.288 |
| 384 | 12.288 | 24.576 |