ZHCSPD4A April 2022 – September 2022 PCM3120-Q1
PRODUCTION DATA
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| STANDARD-MODE | |||||
| fSCL | SCL clock frequency | 0 | 100 | kHz | |
| tHD;STA | Hold time (repeated) START condition. After this period, the first clock pulse is generated. |
4 | μs | ||
| tLOW | Low period of the SCL clock | 4.7 | μs | ||
| tHIGH | High period of the SCL clock | 4 | μs | ||
| tSU;STA | Setup time for a repeated START condition | 4.7 | μs | ||
| tHD;DAT | Data hold time | 0 | 3.45 | μs | |
| tSU;DAT | Data setup time | 250 | ns | ||
| tr | SDA and SCL rise time | 1000 | ns | ||
| tf | SDA and SCL fall time | 300 | ns | ||
| tSU;STO | Setup time for STOP condition | 4 | μs | ||
| tBUF | Bus free time between a STOP and START condition | 4.7 | μs | ||
| FAST-MODE | |||||
| fSCL | SCL clock frequency | 0 | 400 | kHz | |
| tHD;STA | Hold time (repeated) START condition. After this period, the first clock pulse is generated. |
0.6 | μs | ||
| tLOW | Low period of the SCL clock | 1.3 | μs | ||
| tHIGH | High period of the SCL clock | 0.6 | μs | ||
| tSU;STA | Setup time for a repeated START condition | 0.6 | μs | ||
| tHD;DAT | Data hold time | 0 | 0.9 | μs | |
| tSU;DAT | Data setup time | 100 | ns | ||
| tr | SDA and SCL rise time | 20 | 300 | ns | |
| tf | SDA and SCL fall time | 20 × (IOVDD / 5.5 V) | 300 | ns | |
| tSU;STO | Setup time for STOP condition | 0.6 | μs | ||
| tBUF | Bus free time between a STOP and START condition | 1.3 | μs | ||
| FAST-MODE PLUS | |||||
| fSCL | SCL clock frequency | 0 | 1000 | kHz | |
| tHD;STA | Hold time (repeated) START condition. After this period, the first clock pulse is generated. |
0.26 | μs | ||
| tLOW | Low period of the SCL clock | 0.5 | μs | ||
| tHIGH | High period of the SCL clock | 0.26 | μs | ||
| tSU;STA | Setup time for a repeated START condition | 0.26 | μs | ||
| tHD;DAT | Data hold time | 0 | μs | ||
| tSU;DAT | Data setup time | 50 | ns | ||
| tr | SDA and SCL rise time | 120 | ns | ||
| tf | SDA and SCL fall time | 20 × (IOVDD / 5.5 V) | 120 | ns | |
| tSU;STO | Setup time for STOP condition | 0.26 | μs | ||
| tBUF | Bus free time between a STOP and START condition | 0.5 | μs | ||