ZHCSPD4A April 2022 – September 2022 PCM3120-Q1
PRODUCTION DATA
In sleep mode or software shutdown mode, the device consumes very low quiescent current from the AVDD supply and, at the same time, allows the I2C communication to wake the device for active operation.
The device enters sleep mode when the host device sets the SLEEP_ENZ (P0_R2_D0) bit to 1'b0. If the SLEEP_ENZ bit is asserted low when the device is in active mode, the device ramps down the volume on the record data, powers down the analog and digital blocks, and enters sleep mode. However, the device still continues to retain the last programmed value of the device configuration registers and programmable coefficients.
In sleep mode, do not perform any I2C transactions, except for exiting sleep mode in order to enter active mode. After entering sleep mode, wait at least 10 ms before starting I2C transactions to exit sleep mode.
When exiting sleep mode, the host device must configure the PCM3120-Q1 to use either an external 1.8-V AREG supply (default setting) or an on-chip-regulator-generated AREG supply. To configure the AREG supply, write to AREG_SELECT, bit D7 in the same P0_R2 register.