ZHCSPD4A April 2022 – September 2022 PCM3120-Q1
PRODUCTION DATA
The device record channel includes a high dynamic range, built-in digital decimation filter to process the oversampled data from the multibit delta-sigma (ΔΣ) modulator to generate digital data at the same Nyquist sampling rate as the FSYNC rate. As illustrated in Figure 8-16, this decimation filter can also be used for processing the oversampled PDM stream from the digital microphone. The decimation filter can be chosen from three different types, depending on the required frequency response, group delay, and phase linearity requirements for the target application. The selection of the decimation filter option can be done by configuring the DECI_FILT (P0_R107_D[5:4]) register bits. Table 8-22 shows the configuration register setting for the decimation filter mode selection for the record channel.
| P0_R107_D[5:4] : DECI_FILT[1:0] | DECIMATION FILTER MODE SELECTION |
|---|---|
| 00 (default) | Linear phase filters are used for the decimation |
| 01 | Low latency filters are used for the decimation |
| 10 | Ultra-low latency filters are used for the decimation |
| 11 | Reserved (do not use this setting) |