ZHCSPD4A April 2022 – September 2022 PCM3120-Q1
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings
- 7.3 Recommended Operating Conditions
- Thermal Information
- 7.4 Electrical Characteristics
- 7.5 Timing Requirements:?I2C Interface
- 7.6 Switching Characteristics: I2C Interface
- 7.7 Timing Requirements:?TDM, I2S or LJ Interface
- 7.8 Switching Characteristics: TDM, I2S or LJ Interface
- Timing Requirements:?PDM Digital Microphone Interface
- 7.9 Switching Characteristics: PDM Digial Microphone Interface
- 7.10 Timing Diagrams
- 7.11 Typical Characteristics
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Serial Interfaces
- 8.3.2 Phase-Locked Loop (PLL) and Clock Generation
- 8.3.3 Input Channel Configurations
- 8.3.4 Reference Voltage
- 8.3.5 Programmable Microphone Bias
- 8.3.6
Signal-Chain Processing
- 8.3.6.1 Programmable Channel Gain and Digital Volume Control
- 8.3.6.2 Programmable Channel Gain Calibration
- 8.3.6.3 Programmable Channel Phase Calibration
- 8.3.6.4 Programmable Digital High-Pass Filter
- 8.3.6.5 Programmable Digital Biquad Filters
- 8.3.6.6 Programmable Channel Summer and Digital Mixer
- 8.3.6.7
Configurable Digital Decimation Filters
- 8.3.6.7.1
Linear Phase Filters
- 8.3.6.7.1.1 Sampling Rate: 7.35 kHz to 8 kHz
- 8.3.6.7.1.2 Sampling Rate: 14.7 kHz to 16 kHz
- 8.3.6.7.1.3 Sampling Rate: 22.05 kHz to 24 kHz
- 8.3.6.7.1.4 Sampling Rate: 29.4 kHz to 32 kHz
- 8.3.6.7.1.5 Sampling Rate: 44.1 kHz to 48 kHz
- 8.3.6.7.1.6 Sampling Rate: 88.2 kHz to 96 kHz
- 8.3.6.7.1.7 Sampling Rate: 176.4 kHz to 192 kHz
- 8.3.6.7.1.8 Sampling Rate: 352.8 kHz to 384 kHz
- 8.3.6.7.1.9 Sampling Rate: 705.6 kHz to 768 kHz
- 8.3.6.7.2 Low-Latency Filters
- 8.3.6.7.3
Ultra-Low Latency Filters
- 8.3.6.7.3.1 Sampling Rate: 14.7 kHz to 16 kHz
- 8.3.6.7.3.2 Sampling Rate: 22.05 kHz to 24 kHz
- 8.3.6.7.3.3 Sampling Rate: 29.4 kHz to 32 kHz
- 8.3.6.7.3.4 Sampling Rate: 44.1 kHz to 48 kHz
- 8.3.6.7.3.5 Sampling Rate: 88.2 kHz to 96 kHz
- 8.3.6.7.3.6 Sampling Rate: 176.4 kHz to 192 kHz
- 8.3.6.7.3.7 Sampling Rate: 352.8 kHz to 384 kHz
- 8.3.6.7.1
Linear Phase Filters
- 8.3.7 Automatic Gain Controller (AGC)
- 8.3.8 Voice Activity Detection (VAD)
- 8.3.9 Digital PDM Microphone Record Channel
- 8.3.10 Interrupts, Status, and Digital I/O Pin Multiplexing
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6 Register Maps
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
8.3.1.2.2 Inter IC Sound (I2S) Interface
The standard I2S protocol is defined for only two channels: left and right. The device extends the same protocol timing for multichannel operation. In I2S mode, the MSB of the left slot 0 is transmitted on the falling edge of BCLK in the second cycle after the falling edge of FSYNC. Immediately after the left slot 0 data transmission, the remaining left slot data are transmitted in order. The MSB of the right slot 0 is transmitted on the falling edge of BCLK in the second cycle after the rising edge of FSYNC. Immediately after the right slot 0 data transmission, the remaining right slot data are transmitted in order. FSYNC and each data bit is transmitted on the falling edge of BCLK. Figure 8-5 to Figure 8-8 illustrate the protocol timing for I2S operation with various configurations.
Figure 8-5 I2S Mode Standard Protocol Timing (TX_OFFSET = 0)
Figure 8-6 I2S Protocol Timing (TX_OFFSET = 1)
Figure 8-7 I2S Protocol Timing (No Idle BCLK Cycles, TX_OFFSET = 0)
Figure 8-8 I2S Protocol Timing (TX_OFFSET = 0 and BCLK_POL = 1)For proper operation of the audio bus in I2S mode, the number of bit clocks per frame must be greater than or equal to the number of active output channels (including left and right slots) times the programmed word length of the output channel data. The device FSYNC low pulse must be a number of BCLK cycles wide that is greater than or equal to the number of active left slots times the data word length configured. Similarly, the FSYNC high pulse must be a number of BCLK cycles wide that is greater than or equal to the number of active right slots times the data word length configured.