ZHCSJ72A December 2018 – December 2021 OPT3004
PRODMIX
The transparent hysteresis-style comparison mode is typically used when a single digital signal is desired that indicates whether the input light is higher than or lower than a light level of interest. If the result register is higher than the high-limit register for a consecutive number of events set by the fault count field, the INT line is set to active, the flag high field is set to 1, and the flag low field is set to 0. If the result register is lower than the low-limit register for a consecutive number of events set by the fault count field, the INT line is set to inactive, the flag low field is set to 1, and the flag high field is set to 0. The INT pin and flag high and flag low fields do not change state with configuration reads and writes. The INT pin and flag fields continually report the appropriate comparison of the light to the low-limit and high-limit registers. The device does not respond to the SMBus alert response protocol while in either of the two transparent comparison modes (configuration register, latch field = 0). The behavior of this mode, along with the conversion ready is summarized in Table 8-3. Note that Table 8-3 does not apply when the two threshold low register MSBs (LE[3:2] from Table 8-11) are set to 11.
| OPERATION | FLAG HIGH FIELD | FLAG LOW FIELD | INT PIN(1) | CONVERSION READY FIELD |
|---|---|---|---|---|
| The result register is above the high-limit register for fault count times. See the Result Register and the High-Limit Register for further details. | 1 | 0 | Active | 1 |
| The result register is below the low-limit register for fault count times. See the Result Register and the Low-Limit Register for further details. | 0 | 1 | Inactive | 1 |
| The conversion is complete with fault count criterion not met | X | X | X | 1 |
| Configuration register read(3) | X | X | X | 0 |
| Configuration register write, M[1:0] = 00b (shutdown) | X | X | X | X |
| Configuration register write, M[1:0] > 00b (not shutdown) | X | X | X | 0 |
| SMBus alert response protocol | X | X | X | X |