ZHCSJ72A December 2018 – December 2021 OPT3004
PRODMIX
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 說明（續(xù)）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6
Register Maps
- 8.6.1 Internal Registers
- 8.6.2
Register Descriptions
- 8.6.2.1 Result Register (offset = 00h)
- 8.6.2.2 Configuration Register (offset = 01h) [reset = C810h]
- 8.6.2.3 Low-Limit Register (offset = 02h) [reset = C0000h]
- 8.6.2.4 High-Limit Register (offset = 03h) [reset = BFFFh]
- 8.6.2.5 Manufacturer ID Register (offset = 7Eh) [reset = 5449h]
- 8.6.2.6 Device ID Register (offset = 7Fh) [reset = 3001h]
- 9 Application and Implementation
- 10Power-Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
7.6 Timing Requirements
see note (1)
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| I2C FAST MODE | |||||
| fSCL | SCL operating frequency | 0.01 | 0.4 | MHz | |
| tBUF | Bus free time between stop and start | 1300 | ns | ||
| tHDSTA | Hold time after repeated start | 600 | ns | ||
| tSUSTA | Setup time for repeated start | 600 | ns | ||
| tSUSTO | Setup time for stop | 600 | ns | ||
| tHDDAT | Data hold time | 20 | 900 | ns | |
| tSUDAT | Data setup time | 100 | ns | ||
| tLOW | SCL clock low period | 1300 | ns | ||
| tHIGH | SCL clock high period | 600 | ns | ||
| tRC and tFC | Clock rise and fall time | 300 | ns | ||
| tRD and tFD | Data rise and fall time | 300 | ns | ||
| tTIMEO | Bus timeout period. If the SCL line is held low for this duration of time, the bus state machine is reset. | 28 | ms | ||
| I2C HIGH-SPEED MODE | |||||
| fSCL | SCL operating frequency | 0.01 | 2.6 | MHz | |
| tBUF | Bus free time between stop and start | 160 | ns | ||
| tHDSTA | Hold time after repeated start | 160 | ns | ||
| tSUSTA | Setup time for repeated start | 160 | ns | ||
| tSUSTO | Setup time for stop | 160 | ns | ||
| tHDDAT | Data hold time | 20 | 140 | ns | |
| tSUDAT | Data setup time | 20 | ns | ||
| tLOW | SCL clock low period | 240 | ns | ||
| tHIGH | SCL clock high period | 60 | ns | ||
| tRC and tFC | Clock rise and fall time | 40 | ns | ||
| tRD and tFD | Data rise and fall time | 80 | ns | ||
| tTIMEO | Bus timeout period. If the SCL line is held low for this duration of time, the bus state machine is reset. | 28 | ms | ||
(1) All timing parameters are referenced to low and high voltage thresholds of 30% and 70%, respectively, of final settled value.
Figure 7-1 I2C Detailed Timing Diagram