The I2C peripheral in MCF8316C-Q1 implements clock stretching under certain
conditions when there are pending I2C interrupts waiting to be processed.
During clock stretching, MCF8316C-Q1 pulls SCL low and the
I2C bus is unavailable for use by other devices. The following is a
list of conditions under which clock stretching can occur:
- Start interrupt pending:
There are two scenarios when a start interrupt can result in clock stretching,
- When target ID is a
match, I2C peripheral in MCF8316C-Q1 raises a start interrupt request. Until this start
interrupt request is processed, clock is stretched. Upon processing this
request, clock is released and an ACK (marked in yellow or grey in Figure 7-54 and Figure 7-55) is sent to the controller for continuing with the
transaction.
- If Start (followed by
target ID match) for a new transaction is received when a receive
interrupt from previous transaction is yet to be processed, clock is
stretched until both the receive interrupt and start interrupt are
processed in chronological order. This process ensures that previous
transaction is executed correctly before initiating the next
transaction.
- Receive interrupt pending:
When a receive interrupt is waiting to be processed and the receive register is
full which occurs when two successive bytes (data or control) have been received
by MCF8316C-Q1 (separated by one ACK shown as blue
boxes in Figure 7-54 and Figure 7-55) without the receive interrupt generated by the first byte
being processed. Upon receive of second byte, clock is stretched until receive
interrupt generated by the first byte is processed.
- Transmit buffer is empty:
In case of a transmit interrupt pending (to send data back to controller), if
the transmit buffer is waiting to be populated with data to be read back to the
controller, clock stretching is done until the transmit buffer is populated with
requested data. After the buffer is populated, clock is released and data is
sent to controller.
Note: I2C clock stretching is
timed out after 5 ms by MCF8316C-Q1 to allow
I2C bus access for other devices on the same bus.