ZHCSSV1 august 2023 MCF8316C-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Output Stage
- 7.3.2 Device Interface
- 7.3.3 Step-Down Mixed-Mode Buck Regulator
- 7.3.4 AVDD Linear Voltage Regulator
- 7.3.5 Charge Pump
- 7.3.6 Slew Rate Control
- 7.3.7 Cross Conduction (Dead Time)
- 7.3.8 Motor Control Input Sources
- 7.3.9 Starting the Motor Under Different Initial Conditions
- 7.3.10 Motor Start Sequence (MSS)
- 7.3.11 Closed Loop Operation
- 7.3.12 Motor Parameters
- 7.3.13 Motor Parameter Extraction Tool (MPET)
- 7.3.14 Anti-Voltage Surge (AVS)
- 7.3.15 Active Braking
- 7.3.16 Output PWM Switching Frequency
- 7.3.17 PWM Modulation Schemes
- 7.3.18 Dead Time Compensation
- 7.3.19 Motor Stop Options
- 7.3.20 FG Configuration
- 7.3.21 DC Bus Current Limit
- 7.3.22
Protections
- 7.3.22.1 VM Supply Undervoltage Lockout
- 7.3.22.2 AVDD Undervoltage Lockout (AVDD_UV)
- 7.3.22.3 BUCK Under Voltage Lockout (BUCK_UV)
- 7.3.22.4 VCP Charge Pump Undervoltage Lockout (CPUV)
- 7.3.22.5 Overvoltage Protection (OVP)
- 7.3.22.6 Overcurrent Protection (OCP)
- 7.3.22.7 Buck Overcurrent Protection
- 7.3.22.8 Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
- 7.3.22.9 Lock Detection Current Limit (LOCK_ILIMIT)
- 7.3.22.10 FET Thermal Warning (OTW)
- 7.3.22.11 FET Thermal Shutdown (TSD_FET)
- 7.3.22.12 Motor Lock (MTR_LCK)
- 7.3.22.13 Motor Lock Detection
- 7.3.22.14 MPET Faults
- 7.3.22.15 IPD Faults
- 7.4 Device Functional Modes
- 7.5 External Interface
- 7.6 EEPROM access and I2C interface
- 7.7 EEPROM (Non-Volatile) Register Map
- 7.8 RAM (Volatile) Register Map
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
7.6.2.2 I2C Write Transaction
MCF8316C-Q1 write transaction over I2C involves the following sequence (see Figure 7-54).
- I2C start condition.
- Start is followed by the I2C target ID byte, made up of 7-bit target ID along with the R/W bit set to 0b. ACK in yellow box indicates that MCF8316C-Q1 has processed the received target ID which has matched with it's I2C target ID and therefore will proceed with this transaction. If target ID received does not match with the I2C ID of MCF8316C-Q1, then the transaction is ignored. and no ACK is sent by MCF8316C-Q1.
- The target ID byte is followed by the 24-bit control word sent one byte at a time. Bit 23 in the control word is 0b as it is a write transaction. ACK in blue boxes correspond to acknowledgements sent by MCF8316C-Q1 to the controller that the previous byte (of control word) has been received and next byte can be sent.
- The 24-bit control word is
then followed by the data bytes. The number of data bytes sent by the
controller depends on the DLEN field in the control word.
- While sending data bytes, the LSB byte is sent first. Refer to Section 7.6.2.4 for more details.
- 16-bit/32-bit write – The data sent is written to the address mentioned in control word.
- 64-bit Write – 64-bit is treated as two successive 32-bit writes. The address mentioned in control word is taken as Addr_1. Addr_2 is internally calculated by MCF8316C-Q1 by incrementing Addr_1 by 0x2. A total of 8 data bytes are sent. The first 4 bytes (sent in LSB first) are written to Addr_1 and the next 4 bytes are written to Addr_2.
- ACK in blue boxes (after every data byte) correspond to the acknowledgement sent by MCF8316C-Q1 to the controller that the previous data byte has been received and next data byte can be sent.
- If CRC is enabled, the packet ends with a CRC byte. CRC is calculated for the entire packet (Target ID + W bit, Control Word, Data Bytes). MCF8316C-Q1 will send an ACK on receiving the CRC byte.
- I2C Stop condition from the controller to terminate the transaction.
Figure 7-54 I2C Write Transaction Sequence