ZHCSKL3C December 2019 – May 2024 LP8866-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| LOGIC INPUT EN | ||||||
| VENIL | EN logic low threshold | 0.4 | V | |||
| VENIH | EN logic high threshold | 1.2 | V | |||
| RENPD | EN pin internal pull down resistance | 1 | MΩ | |||
| LOGIC INPUT SDA, SCL, BST_SYNC and PWM | ||||||
| VIL | Logic low threshold | VDD = 3.3V and 5V | 0.4 | V | ||
| VIH | Logic high threshold | VDD = 3.3V and 5V | 1.2 | V | ||
| LOGIC OUTPUT SDA, INT | ||||||
| VOL | Output level low | I = 3mA | 0.2 | 0.4 | V | |
| ILEAKAGE | Output leakage current | V = 3.3V | 1 | μA | ||