ZHCSKL3C December 2019 – May 2024 LP8866-Q1
PRODUCTION DATA
If during LP8866-Q1 device operation VDD falls below VDDUVLO falling level, boost, power-line FET, and LED outputs are turned off, and the device enters STANDBY mode. The VDDUVLO_STATUS fault bit will be set in the SUPPLY_FAULT_STATUS register, and the INT pin will be triggered. The LP8866-Q1 restarts automatically to ACTIVE mode when VDD rises above VDDUVLO rising threshold.