ZHCSGN5B March 2017 – July 2018 LP8863-Q1
PRODUCTION DATA.
In SPI mode host can address as many unique LP8863-Q1 devices as there are slave select pins on host. The complete 10-bit register space in LP8863-Q1 device can be accessed using SPI interface.
The LP8863-Q1 device is compatible with SPI serial-bus specification and operates as a slave device. The transmission consists of 32-bit write and read cycles. One cycle consists of a 15-bit register address (10 bits used), 1 read/write (R/W) bit and 16-bit data to maintain compatibility with 16-bit SPI.
The R/W bit high state defines a write cycle and low defines a read cycle. The SDO output is normally in a high-impedance state. When the slave-select pin SS for the device is active (that is, low) the SDO output is pulled low. During write cycle SDO stays in high-impedance state. The address and data bits are transmitted MSB first. The slave-select signal SS must be low during the cycle transmission. SS resets the interface when high, and it has to be taken high between successive cycles, except when using auto- increment mode. Data is clocked in on the rising edge of the SCLK clock signal, while data is clocked out on the falling edge of SCLK.
Figure 30. SPI Write
Figure 31. SPI Read