SNVSBP2 February 2020 LP8758-E3
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6
Register Maps
- 7.6.1
Register Descriptions
- 7.6.1.1 OTP_REV
- 7.6.1.2 BUCK0_CTRL1
- 7.6.1.3 BUCK0_CTRL2
- 7.6.1.4 BUCK1_CTRL1
- 7.6.1.5 BUCK1_CTRL2
- 7.6.1.6 BUCK2_CTRL1
- 7.6.1.7 BUCK2_CTRL2
- 7.6.1.8 BUCK3_CTRL1
- 7.6.1.9 BUCK3_CTRL2
- 7.6.1.10 BUCK0_VOUT
- 7.6.1.11 BUCK0_FLOOR_VOUT
- 7.6.1.12 BUCK1_VOUT
- 7.6.1.13 BUCK1_FLOOR_VOUT
- 7.6.1.14 BUCK2_VOUT
- 7.6.1.15 BUCK2_FLOOR_VOUT
- 7.6.1.16 BUCK3_VOUT
- 7.6.1.17 BUCK3_FLOOR_VOUT
- 7.6.1.18 BUCK0_DELAY
- 7.6.1.19 BUCK1_DELAY
- 7.6.1.20 BUCK2_DELAY
- 7.6.1.21 BUCK3_DELAY
- 7.6.1.22 RESET
- 7.6.1.23 CONFIG
- 7.6.1.24 INT_TOP
- 7.6.1.25 INT_BUCK_0_1
- 7.6.1.26 INT_BUCK_2_3
- 7.6.1.27 TOP_STAT
- 7.6.1.28 BUCK_0_1_STAT
- 7.6.1.29 BUCK_2_3_STAT
- 7.6.1.30 TOP_MASK
- 7.6.1.31 BUCK_0_1_MASK
- 7.6.1.32 BUCK_2_3_MASK
- 7.6.1.33 SEL_I_LOAD
- 7.6.1.34 I_LOAD_2
- 7.6.1.35 I_LOAD_1
- 7.6.1
Register Descriptions
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
7.3.5.1.1 Output Current Limit
The converter cores have programmable output peak current limits. The limits are individually programmed for all buck converter cores with BUCKx_CTRL2.ILIMx[2:0] bits. If the load current is increased so that the current limit is triggered, the regulator continues to regulate to the limit current level (current peak regulation). The voltage may decrease if the load current is higher than limit current. If the current regulation continues for 20 µs, the LP8758-E3 device sets the INT_BUCKx.BUCKx_ILIM_INT bit and pulls the nINT pin low. The host processor can read BUCKx_STAT.BUCKx_ILIM_STAT bits to see if the converter cores is still in peak current regulation mode.
For example, if the load on Buck0 output is so high that the output voltage VOUT decreases below a 350-mV level, the LP8758-E3 device disables the converter core Buck0 and sets the INT_BUCK_0_1.BUCK0_SC_INT bit. In addition the BUCK_0_1_STAT.BUCK0_STAT bit is set to 0. The interrupt is cleared when the host processor writes 1 to INT_BUCK_0_1.BUCK0_SC_INT bit. The overload situation is shown in Figure 11.
Figure 11. Overload Situation