ZHCSHY8 March 2018 LP87561-Q1 , LP87562-Q1 , LP87563-Q1 , LP87564-Q1 , LP87565-Q1
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
Address: 0x2B
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| PLL_MODE[1:0] | Reserved | EXT_CLK_FREQ[4:0] | |||||
| Bits | Field | Type | Default | Description |
|---|---|---|---|---|
| 7:6 | PLL_MODE[1:0] | R/W | X | This bit selects the external clock and PLL operation.
0h = Forced to internal RC oscillator (PLL is disabled). 1h = PLL is enabled in the STANDBY and ACTIVE states. Automatic external clock use when available, interrupt generated if external clock appears or disappears. 2h = PLL is enabled only in the ACTIVE state. Automatic external clock use when available, interrupt generated if external clock appears or disappears. 3h = Reserved |
| 5 | Reserved | R/W | 0 | |
| 4:0 | EXT_CLK_FREQ[4:0] | R/W | X | Frequency of the external clock (CLKIN). For the input clock frequency tolerance see the Electrical Characteristics table. Settings 18h through 1Fh are reserved and must not be used.
0x00h = 1 MHz 0x01h = 2 MHz 2h = 3 MHz 16h = 23 MHz 17h = 24 MHz . |