ZHCSHY8 March 2018 LP87561-Q1 , LP87562-Q1 , LP87563-Q1 , LP87564-Q1 , LP87565-Q1
PRODUCTION DATA.
Address: 0x2A
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| Reserved | PG3_FLT | PG2_FLT | PG1_FLT | PG0_FLT | |||
| Bits | Field | Type | Default | Description |
|---|---|---|---|---|
| 7:4 | Reserved | R/W | 0x0 | |
| 3 | PG3_FLT | R | 0 | Source for the PGOOD inactive signal
0h = BUCK3 has not set the PGOOD signal inactive. 1h = BUCK3 has set the PGOOD signal inactive. This bit can be cleared by reading this register when the BUCK3 output is valid. |
| 2 | PG2_FLT | R | 0 | Source for the PGOOD inactive signal
0h = BUCK2 has not set the PGOOD signal inactive. 1h = BUCK2 has set the PGOOD signal inactive. This bit can be cleared by reading this register when the BUCK2 output is valid. |
| 1 | PG1_FLT | R | 0 | Source for the PGOOD inactive signal
0h = BUCK1 has not set the PGOOD signal inactive. 1h = BUCK1 has set the PGOOD signal inactive. This bit can be cleared by reading this register when the BUCK1 output is valid. |
| 0 | PG0_FLT | R | 0 | Source for the PGOOD inactive signal
0h = BUCK0 has not set the PGOOD signal inactive. 1h = BUCK0 has set the PGOOD signal inactive. This bit can be cleared by reading this register when the BUCK0 output is valid. |