ZHCSHY8 March 2018 LP87561-Q1 , LP87562-Q1 , LP87563-Q1 , LP87564-Q1 , LP87565-Q1
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
Address: 0x28
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| PG3_SEL[1:0] | PG2_SEL[1:0] | PG1_SEL[1:0] | PG0_SEL[1:0] |
| Bits | Field | Type | Default | Description |
|---|---|---|---|---|
| 7:6 | PG3_SEL[1:0] | R/W | X | PGOOD signal source control from the BUCK3 regulator
0h = Masked 1h = Power-good-threshold voltage 2h = Reserved, do not use 3h = Power-good-threshold voltage AND current limit |
| 5:4 | PG2_SEL[1:0] | R/W | X | PGOOD signal source control from the BUCK2 regulator
0h = Masked 1h = Power-good-threshold voltage 2h = Reserved, do not use 3h = Power-good threshold voltage AND current limit |
| 3:2 | PG1_SEL[1:0] | R/W | X | PGOOD signal source control from the BUCK1 regulator
0h = Masked 1h = Power-good-threshold voltage 2h = Reserved, do not use 3h = Power-good-threshold voltage AND current limit |
| 1:0 | PG0_SEL[1:0] | R/W | X | PGOOD signal source control from the BUCK0 regulator
0h = Masked 1h = Power-good-threshold voltage 2h = Reserved, do not use 3h = Power-good-threshold voltage AND current limit |