ZHCSBC7E JULY 2013 – December 2019 LMZ31710
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 VIN and PVIN Input Voltage
- 7.3.2 3.3-V PVIN Operation
- 7.3.3 Adjusting the Output Voltage (0.6 V to 5.5 V)
- 7.3.4 Capacitor Recommendations For the LMZ31710 Power Supply
- 7.3.5 Transient Response
- 7.3.6 Power Good (PWRGD)
- 7.3.7 Light Load Efficiency (LLE)
- 7.3.8 SYNC_OUT
- 7.3.9 Parallel Operation
- 7.3.10 Power-Up Characteristics
- 7.3.11 Pre-Biased Start-Up
- 7.3.12 Remote Sense
- 7.3.13 Thermal Shutdown
- 7.3.14 Output On/Off Inhibit (INH)
- 7.3.15 Slow Start (SS/TR)
- 7.3.16 Overcurrent Protection
- 7.3.17 Synchronization (CLK)
- 7.3.18 Sequencing (SS/TR)
- 7.4 Device Functional Modes
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
7.4.1 Programmable Undervoltage Lockout (UVLO)
The LMZ31710 implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO rising threshold is 4.5 V(max) with a typical hysteresis of 150 mV.
If an application requires either a higher UVLO threshold on the VIN pin or a higher UVLO threshold for a combined VIN and PVIN, then the UVLO pin can be configured as shown in Figure 39 or Figure 40. Table 8 lists standard values for RUVLO1 and RUVLO2 to adjust the VIN UVLO voltage up.
Figure 39. Adjustable VIN UVLO 
Figure 40. Adjustable VIN And Pvin Undervoltage Lockout Table 8. Standard Resistor Values For Adjusting VIN UVLO
| VIN UVLO (V) | 5 | 5.5 | 6 | 6.5 | 7 | 7.5 | 8 | 8.5 | 9 | 9.5 | 10 |
|---|---|---|---|---|---|---|---|---|---|---|---|
| RUVLO1 (kΩ) | 68.1 | 68.1 | 68.1 | 68.1 | 68.1 | 68.1 | 68.1 | 68.1 | 68.1 | 68.1 | 68.1 |
| RUVLO2 (kΩ) | 21.5 | 18.7 | 16.9 | 15.4 | 14.0 | 13.0 | 12.1 | 11.3 | 10.5 | 9.76 | 9.31 |
| Hysteresis (mV) | 400 | 415 | 430 | 450 | 465 | 480 | 500 | 515 | 530 | 550 | 565 |
For a split rail application, if a secondary UVLO on PVIN is required, VIN must be ≥ 4.5 V. Figure 41 shows the PVIN UVLO configuration. Use Table 9 to select RUVLO1 and RUVLO2 for PVIN. If PVIN UVLO is set for less than 3.5 V, a 5.1-V zener diode must be added to clamp the voltage on the UVLO pin below 6 V.
Figure 41. Adjustable PVIN Undervoltage Lockout, (VIN ≥ 4.5 V) Table 9. Standard Resistor Values For Adjusting Pvin UVLO, (VIN ≥ 4.5 V)
| PVIN UVLO (V) | 2.9 | 3.0 | 3.5 | 4.0 | 4.5 | |
|---|---|---|---|---|---|---|
| RUVLO1 (kΩ) | 68.1 | 68.1 | 68.1 | 68.1 | 68.1 | For higher PVIN UVLO voltages, see Table 8 for resistor values |
| RUVLO2 (kΩ) | 47.5 | 44.2 | 34.8 | 28.7 | 24.3 | |
| Hysteresis (mV) | 330 | 335 | 350 | 365 | 385 |