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ZHCSIZ1G May 2010 – November 2018 LM98640QML-SP

PRODUCTION DATA.

封裝選項

請參考 PDF 數據表獲取器件具體的封裝圖。

機械數據 (封裝 | 引腳)

NBB|68

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

5 Pin Configuration and Functions

68-Pin QFP

Package NBB0068D

Top View

Pin Functions

PIN	NAME	I/O⁽¹⁾	TYP	RES	DESCRIPTION
1	VCOM1	O	A		Common mode of ADC reference. Bypass with 0.1-µF capacitor to VSS33.
2	VDD33		P		Analog power supply. Decouple with minimum 0.1-µF capacitor to VSS33 plane.
3	VDD33		P		Analog power supply. Decouple with minimum 0.1-µF capacitor to VSS33 plane.
4	VSS33		P		Analog supply return.
5	VSS33		P		Analog supply return.
6	OS1-	I	A		Analog input signal.
7	OS1+	I	A		Sample/Hold Mode Reference Level. Bypassed with a 0.1-µF to ground in CDS mode.
8	VSS33		P		Analog supply return.
9	VCLP	O	A		Programmable Clamp Voltage output. Normally bypassed with a 0.1-µF capacitor to VSS33.
10	VSS33		P		Analog supply return.
11	OS2+	I	A		Sample/Hold Mode Reference Level. Bypassed with a 0.1-µF to ground in CDS mode.
12	OS2-	I	A		Analog input signal.
13	VSS33		P		Analog supply return.
14	VSS33		P		Analog supply return.
15	VDD33		P		Analog power supply. Decouple with minimum 0.1-µF capacitor to VSS33 plane.
16	VDD33		P		Analog power supply. Decouple with minimum 0.1-µF capacitor to VSS33 plane.
17	VCOM2	O	A		Common mode of ADC reference. Bypass with 0.1-µF capacitor to ground.
18	VREFB2	O	A		Bottom of ADC reference. Bypass with a 0.1-µF capacitor to ground.
19	VREFT2	O	A		Top of ADC reference. Bypass with a 0.1-µF capacitor to ground.
20	VSS33		P		Analog supply return.
21	VSS33		P		Analog supply return.
22	VDD33		P		Analog power supply. Decouple with minimum 0.1-µF capacitor to VSS33 plane.
23	VDD33		P		Analog power supply. Decouple with minimum 0.1-µF capacitor to VSS33 plane.
24	VSS33		P		Analog supply return.
25	SDO	O	D		Serial Interface Data Output. (Tri-State when SEN is high)
26	SDI	I	D		Serial Interface Data Input. (Tri-State when SEN is high)
27	SCLK	I	D	PD	Serial Interface shift register clock. (Tri-State when SEN is high)
28	SEN	I	D	PU	Active-low chip enable for the Serial Interface.
29	NC				No Connection. Can be connected to VSS18.
30	CLPIN	I	D		Input clamp signal.
31	VSS18		P		Digital supply return.
32	VDD18		P		Digital power supply. Decouple with minimum 0.1-µF capacitor to VSS18 plane.
33	DTM1	O	D		Digital Timing Monitor. If not used, can be connected to VDD18 through a 10-kΩ resistor.
34	DTM0	O	D		Digital Timing Monitor. If not used, can be connected to VDD18 through a 10-kΩ resistor.
35	VDD18		P		Digital power supply. Decouple with minimum 0.1-µF capacitor to VSS18 plane.
36	VSS18		P		Digital supply return.
37	TXFRM+	O	D		LVDS Frame+
38	TXFRM-	O	D		LVDS Frame-
39	TXOUT3+	O	D		LVDS Data Out3+
40	TXOUT3-	O	D		LVDS Data Out3-
41	TXOUT2+	O	D		LVDS Data Out2+
42	TXOUT2-	O	D		LVDS Data Out2-
43	TXOUT1+	O	D		LVDS Data Out1+
44	TXOUT1-	O	D		LVDS Data Out1-
45	TXOUT0+	O	D		LVDS Data Out0+
46	TXOUT0-	O	D		LVDS Data Out0-
47	TXCLK+	O	D		LVDS Clock+
48	TXCLK-	O	D		LVDS Clock-
49	VSS18		P		Digital supply return.
50	VDD18		P		Digital power supply. Decouple with minimum 0.1-µF capacitor to VSS18 plane.
51	ATB0	O	A		Analog Test Bus. If not used, can be connected to VSS18 through a 10-kΩ resistor.
52	ATB1	O	A		Analog Test Bus. If not used, can be connected to VSS18 through a 10-kΩ resistor.
53	VDD18		P		Digital power supply. Decouple with minimum 0.1-µF capacitor to VSS18 plane.
54	VDD18		P		Digital power supply. Decouple with minimum 0.1-µF capacitor to VSS18 plane.
55	VSS18		P		Digital supply return.
56	VSS18		P		Digital supply return.
57	INCLK-	I	D		Clock Input. Inverting input for LVDS clocks.
58	INCLK+	I	D		Clock Input. Non-Inverting input for LVDS clocks.
59	VSS33		P		Analog supply return.
60	VDD33		P		Analog power supply. Decouple with minimum 0.1-µF capacitor to VSS33 plane.
61	VDD33		P		Analog power supply. Decouple with minimum 0.1-µF capacitor to VSS33 plane.
62	VSS33		P		Analog supply return.
63	IBIAS0	I	A		Connect with external 10-kΩ 1% resistor to IBIAS1 pin.
64	IBIAS1	I	A		Connect with external 10-kΩ 1% resistor to IBIAS0 pin.
65	VREFBG	O	A		Band gap reference output. Bypass with a 0.1-µF capacitor to VSS33. Can be overdriven with external voltage source.
66	VSS33		P		Analog supply return.
67	VREFT1	O	A		Top of ADC reference. Bypass with a 0.1-µF capacitor to VSS33.
68	VREFB1	O	A		Bottom of ADC reference. Bypass with a 0.1-µF capacitor to VSS33.
	Exp Pad		P		Exposed pad must be soldered to ground plane to ensure rated performance.

(1) (I = Input), (O = Output), (IO = Bi-directional), (P = Power), (D = Digital), (A = Analog), (PU = Pull Up with an internal resistor), (PD = Pull Down with an internal resistor.).