ZHCSIZ1G May 2010 – November 2018 LM98640QML-SP
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | NOTES | SUB-
GROUPS |
MIN | TYP(2) | MAX | UNIT | |
|---|---|---|---|---|---|---|---|---|
| INPUT CLOCK TIMING SPECIFICATIONS | ||||||||
| fINCLK | Input clock frequency | INCLK = ADCCLK | 9, 10, 11 | 5 | 40 | MHz | ||
| (ADC Rate Clock) | ||||||||
| Tdc | Input clock duty cycle | 9, 10, 11 | 40/60% | 50/50% | 60/40% | |||
| tLAT | Pipeline latency | See(1) | 10 | TADC | ||||
| LVDS OUTPUT TIMING SPECIFICATIONS | ||||||||
| tDOD | Data output delay | fINCLK = 40 MHz
INCLK = ADCCLK (ADC Rate Clock) LVDS Output Specifications not tested in production. Min/Max ensured by design, characterization and statistical analysis. |
9, 10, 11 | 6.44 | 7.50 | ns | ||
| tDSO | Dual lane mode | 9, 10, 11 | 0.45 | 0.69 | ns | |||
| Odd data setup | ||||||||
| tDSE | Dual lane mode | 9, 10, 11 | 0.45 | 0.89 | ns | |||
| Even data setup | ||||||||
| tQSR | Quad lane mode | 9, 10, 11 | 0.45 | 0.63 | ns | |||
| Data to rising clock setup | ||||||||
| tQHF | Quad lane mode | 9, 10, 11 | 0,45 | 0.53 | ns | |||
| Falling clock to data hold | ||||||||
| SERIAL INTERFACE TIMING SPECIFICATIONS | ||||||||
| fSCLK | Input clock frequency | fSCLK <= fINCLK | 9, 10, 11 | 1 | 20 | MHz | ||
| INCLK = ADCCLK | ||||||||
| (ADC Rate Clock) | ||||||||
| SCLK duty cycle | 9, 10, 11 | 40/60 | 50/50 | 60/40 | ns | |||
| tIH | Input hold time | 9, 10, 11 | 2.5 | 1 | ns | |||
| tIS | Input setup time | 9, 10, 11 | 2.5 | 1 | ns | |||
| tSENSC | SCLK start time after SEN low | 9, 10, 11 | 1.5 | 1 | ns | |||
| tSCSEN | SEN high after last SCLK rising edge | 9, 10, 11 | 2.5 | 2 | ns | |||
| tSENW | SEN pulse width | 9, 10, 11 | 8 | 6 | ns | |||
| tOD | Output delay time | 9, 10, 11 | 10.54 | 11.6 | ns | |||
| tHZ | Data output to high Z | 9, 10, 11 | 1.2 | 1.23 | TSCLK | |||