ZHCSIZ1G May 2010 – November 2018 LM98640QML-SP
PRODUCTION DATA.
The LM98640QML-SP output includes a frame signal (TXFRM) that should be used to locate the beginning and end of a particular pixel's serial data word. The rising edge of TXFRM is coincident with the pixel's leading bit transition (TXOUT MSB). This TXFRM rising edge can be detected by the capturing FPGA or ASIC to mark the start of the serial data word.
In CDS mode, the input sampling amplifier has two physical paths through which a particular pixel will be sampled. These two sampling paths are a requirement in the Correlated Double Sampling architecture. The sampling of the one pixel will travel the first path (arbitrarily called an even pixel), and the sampling of the next pixel will travel the second path (called an odd pixel). The sampling will continue in an even/odd/even/odd fashion for all pixels processed in a particular channel. Due to slight variances in the sampling paths (most commonly a difference in switched capacitor matching), the processing of identical pixels through the two different paths may result in a small offset in ADC output data between the two paths. To correct this, a simple digital offset can be applied in post processing to either the even pixel data or the odd pixel data. To simplify this action, the LM98640QML-SP will indicate (with the TXFRM signal) whether the pixel traveled the even path or the odd path. For all "Odd" pixels, the TXFRM signal is high for three TXCLK periods. For "Even" pixels, the TXFRM signal is high for two TXCLK periods. In Sample and Hold Mode there is only one sampling path, therefore there is no need to indicate an even or odd pixel. As a result, the TXFRM signal is the same for every pixel in Sample and Hold mode (i.e. high for three TXCLK periods).