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ZHCSKA7F May 2019 – June 2021 LM61460-Q1

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

RJR|14
- MPQF507F

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

8.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature range of -40°C to +150°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at T_J = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: V_IN = 13.5 V. VIN1 shorted to VIN2 = V_IN. V_OUT is converter output voltage.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY VOLTAGE AND CURRENT
V_{IN_OPERATE}	Input operating voltage⁽³⁾	Needed to start up	3.95			V
V_{IN_OPERATE}	Input operating voltage⁽³⁾	Once operating	3.0			V
V_{IN_OPERATE_H}	Hysteresis⁽³⁾			1		V
I_{Q_VIN}	Operating quiescent current (not switching)⁽⁴⁾	V_FB = +5%, V_BIAS = 5 V		9	18	μA
I_Q	Operating quiescent current (not switching); measured at VIN pin⁽¹⁾	V_FB = +5%, V_BIAS = 5 V		0.6	6	μA
I_BIAS	Current into BIAS pin (not switching, maximum at T_J = 125°C)⁽¹⁾	V_FB = +5%, V_BIAS = 5 V, Auto Mode		24	31.2	μA
I_SD	Shutdown quiescent current; measured at VIN pin	EN = 0 V, T_J= 25℃		0.6	6	μA
ENABLE
V_EN	Enable input threshold voltage - rising			1.263		V
V_EN-ACC	Enable input threshold voltage - rising deviation from typical		-5		5	%
V_EN-HYST	Enable threshold hysteresis as percentage of V_EN (TYP)		24	28	32	%
V_EN-WAKE	Enable wake-up threshold		0.4			V
I_EN	Enable pin input current	V_IN = EN = 13.5 V		2.3		nA
V_{EN_SYNC}	Edge height necessary to sync using EN/SYNC pin	Rise/fall time <30 ns			2.4	V
LDO - VCC
V_CC	Internal V_CC voltage	V_BIAS > 3.4 V, CCM Operation⁽³⁾		3.3		V
V_CC	Internal V_CC voltage	V_BIAS = 3.1 V, Non-switching		3.1		V
V_{CC_UVLO}	Internal V_CC input under voltage lock-out	V_CC rising under voltage threshold		3.6		V
V_{CC_UVLO_HYST}	Internal V_CC input under voltage lock-out	Hysteresis below V_{CC_UVLO}		1.1		V
FEEDBACK
V_{FB_acc}	Initial reference voltage accuracy	V_IN = 3.3 V to 36 V, FPWM Mode	-1		1	%
I_FB	Input current from FB to AGND	Adjustable versions only, FB = 1 V		10		nA
OSCILLATOR
f_ADJ	Minimum adjustable frequency by R_T or SYNC	RT = 66.5 k?	0.18	0.2	0.22	MHz
	Adjustable frequency by R_T or SYNC with 400 kHz setting	RT = 33.2 k?	0.36	0.4	0.44	MHz
	Maximum adjustable frequency by R_T or SYNC	RT = 5.76 k?	1.98	2.2	2.42	MHz
f_S _SS	Frequency span of spread spectrum operation - largest deviation from center frequency	Spread spectrum active		2		%
f_PSS	Spread spectrum pattern frequency⁽³⁾	Spread spectrum active, f_SW = 2.1 MHz			1.5	Hz
MOSFETS
R_{DS(ON)_HS}	Power switch on-resistance	High side MOSFET R_DS(ON)		41	82	m?
R_{DS(ON)_LS}	Power switch on-resistance	Low side MOSFET R_DS(ON)		21	45	m?
V_{BOOT_UVLO}	Voltage on CBOOT pin compared to SW which will turn off high-side switch			2.1		V
CURRENT LIMITS
I_L-HS	High side switch current limit⁽²⁾	Duty Cycle approaches 0%	8.9	10.3	11.5	A
I_L-LS	Low side switch current limit		6.1	7.1	8.1	A
I_L-ZC	Zero-cross current limit. Positive current direction is out of SW pin	Auto Mode, static measurement		0.25		A
I_L-NEG	Negative current limit FPWM and SYNC Modes. Positive current direction is out of SW pin.	FPWM operation		-3		A
I_{PK_MIN_0}	Minimum peak command in Auto Mode / device current rating	Pulse duration < 100 ns		25		%
I_{PK_MIN_100}	Minimum peak command in Auto Mode / device current rating	Pulse duration > 1 μs		12.5		%
V_HICCUP	Ratio of FB voltage to in-regulation FB voltage	Not during soft start		40		%
POWER GOOD
PGD_OV	PGOOD upper threshold - rising	% of V_OUTsetting	105	107	110	%
PGD_U _V	PGOOD lower threshold - falling	% of V_OUTsetting	92	94	96.5	%
PGD_HYST	PGOOD upper threshold (rising & falling)	% of V_OUTsetting		1.3		%
V_{IN(PGD_VALID)}	Input voltage for proper PGOOD function		1.0			V
V_PGD(LOW)	Low level PGOOD function output voltage	46 μA pullup to PGOOD pin, V_IN = 1.0 V, EN = 0 V			0.4	V
		1 mA pullup to PGOOD pin, V_IN = 13.5 V, EN = 0 V			0.4
		2 mA pullup to PGOOD pin, V_IN = 13.5 V, EN = 3.3 V			0.4
R_PGD	R_DS(ON) of PGOOD output	1 mA pullup to PGOOD pin, EN = 0 V		17	40	?
R_PGD	R_DS(ON) of PGOOD output	1 mA pullup to PGOOD pin, EN = 3.3 V		40	90	?
I_OV	Pull down current at the SW node under over voltage condition			0.5		mA
THERMAL SHUTDOWN
T_{SD_R}	Thermal shutdown rising threshold⁽³⁾		158	168	180	℃
T_{SD_HYST}	Thermal shutdown hysteresis⁽³⁾			10		℃

(1) This is the current used by the device while not switching, open loop, with FB pulled to +5% of nominal. It does not represent the total input current to the system while regulating. For additional information, reference the Systems Chracaterisitics Table and the Input Supply Current Section.

(2) High side current limit is function of duty factor. High side current limit is highest at small duty factor and less at higher duty factors.

(3) Parameter specified by design, statistical analysis and production testing of correlated parameters.

(4) I_{Q_VIN} = I_Q + I_BIAS × (V_OUT / V_IN)