ZHCSKN8A december 2019 – april 2023 LM5163H-Q1
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Control Architecture
- 7.3.2 Internal VCC Regulator and Bootstrap Capacitor
- 7.3.3 Regulation Comparator
- 7.3.4 Internal Soft Start
- 7.3.5 On-Time Generator
- 7.3.6 Current Limit
- 7.3.7 N-Channel Buck Switch and Driver
- 7.3.8 Synchronous Rectifier
- 7.3.9 Enable/Undervoltage Lockout (EN/UVLO)
- 7.3.10 Power Good (PGOOD)
- 7.3.11 Thermal Protection
- 7.4 Device Functional Modes
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
7.3.6 Current Limit
The LM5163H-Q1 manages overcurrent conditions with cycle-by-cycle current limiting of the peak inductor current. The current sensed in the high-side MOSFET is compared every switching cycle to the current limit threshold (0.75 A). To protect the converter from potential current runaway conditions, the LM5163H-Q1 includes a foldback valley current limit feature set at 0.6 A that is enabled if a peak current limit is detected. As shown in Figure 7-1, if the peak current in the high-side MOSFET exceeds 0.75 A (typical), the present cycle is immediately terminated regardless of the programmed on-time (tON), the high-side MOSFET is turned off and the foldback valley current limit is activated. The low-side MOSFET remains on until the inductor current drops below this foldback valley current limit, after which the next on-pulse is initiated. This method folds back the switching frequency to prevent overheating and limits the average output current to less than 0.75 A to ensure proper short-circuit and heavy-load protection of the LM5163H-Q1.
Figure 7-1 Current Limit Timing
DiagramCurrent is sensed after a leading-edge blanking time following the high-side MOSFET turnon transition. The propagation delay of the current limit comparator is 100 ns. During high step-down conditions when the on-time is less than 100 ns, a back-up peak current limit comparator in the low-side FET also set at 0.75 A enables the foldback valley current limit set at 0.6 A. This innovative current limit scheme enables ultra-low duty-cycle operation, permitting large step-down voltage conversions while ensuring robust protection of the converter.