ZHCSPX4A February 2022 – April 2022 LM5152-Q1 , LM51521-Q1
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 說明（續(xù)）
- 6 Device Comparison Table
- 7 Pin Configuration and Functions
- 8 Specifications
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 Device Enable/Disable (EN, VH Pin)
- 9.3.2 High Voltage VCC Regulator (BIAS, VCC Pin)
- 9.3.3 Light Load Switching Mode Selection (MODE Pin)
- 9.3.4 Line Undervoltage Lockout (UVLO Pin)
- 9.3.5 Fast Restart Using VCC HOLD (VH Pin)
- 9.3.6 Adjustable Output Regulation Target (VOUT, TRK, VREF Pin)
- 9.3.7 Overvoltage Protection (VOUT Pin)
- 9.3.8 Boost Status Indicator (STATUS Pin)
- 9.3.9 Dynamically Programmable Switching Frequency (RT)
- 9.3.10 External Clock Synchronization (SYNC Pin)
- 9.3.11 Programmable Spread Spectrum (DITHER Pin)
- 9.3.12 Programmable Soft Start (SS Pin)
- 9.3.13 Wide Bandwidth Transconductance Error Amplifier and PWM (TRK, COMP Pin)
- 9.3.14 Current Sensing and Slope Compensation (CSP, CSN Pin)
- 9.3.15 Constant Peak Current Limit (CSP, CSN Pin)
- 9.3.16 Maximum Duty Cycle and Minimum Controllable On-Time Limits
- 9.3.17 Deep Sleep Mode and Bypass Operation (HO, CP Pin)
- 9.3.18 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LO, HO, HB Pin)
- 9.3.19 Thermal Shutdown Protection
- 9.4 Device Functional Modes
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
封裝選項
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGR|20
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGR|20
訂購信息
10.2.2.1 Application Ideas
For applications requiring the lowest cost with minimum conduction loss, inductor DC resistance (DCR) can be used to sense the inductor current rather than using a sense resistor. RDCRC and CDCRC must meet Equation 14 to match a time constant.
Figure 10-2 DCR Current Sensing Equation 14.
Add a diode from STATUS to DITHER if the clock dithering is required in active mode and the bypass operation is required in deep sleep mode.
Figure 10-3 Enable Both Clock Dithering and Bypass
Operation