The performance of switching converters heavily depends on the quality of the PCB
layout. The following guidelines will help users design a PCB with the best power
conversion performance, thermal performance, and minimize generation of unwanted
EMI.
- Place CVCC,
CBIAS, CHB, and CVOUT as close to the
device. Make direct connections to the pins.
- Place QH,
QL, and COUT. Make the switching loop (COUT
to QH to QL to COUT) as small as possible. A
small size ceramic capacitor helps to minimize the loop length. Leave a copper
area near the drain connection of QH for a thermal dissipation.
- Place LM,
RS, and CIN. Make the loop (CIN to
RS to LM to CIN) as small as possible. A
small size ceramic capacitor helps to minimize the loop length.
- Connect RS to CSP-CSN.
The CSP-CSN traces must be routed in parallel and surrounded by ground.
- Connect VOUT, HO, and SW. These traces must be routed in
parallel using a short, low inductance path. VOUT must be directly connected the
drain connection of QH. SW must be directly connected to the source
connection of QH
- Connect LO and PGND. The LO-PGND traces must be routed in
parallel using a short, low inductance path. PGND must be directly connected the
source connection of QL
- Place RCOMP, CCOMP, CSS,
CVREF, RVREFT, RVREFB, RT, and
RUVLOB as close to the device, and connect to a common analog
ground plane.
- Connect power ground plane (the source connection of the
QL) to EP through PGND. Connect the common analog ground plane to
EP through AGND. PGND and AGND must be connected underneath the device.
- Add several vias under EP to help
conduct heat away from the device. Connect the vias to a large analog ground
plane on the bottom layer.
- Do not connect COUT
and CIN grounds underneath the device and through the large analog
ground plane which is connected to EP.