ZHCSMW2B December 2021 – December 2022 LM5123-Q1
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 說明（續）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Device Enable/Disable (EN, VH Pin)
- 8.3.2 High Voltage VCC Regulator (BIAS, VCC Pin)
- 8.3.3 Light Load Switching Mode Selection (MODE Pin)
- 8.3.4 VOUT Range Selection (RANGE Pin)
- 8.3.5 Line Undervoltage Lockout (UVLO Pin)
- 8.3.6 Fast Restart using VCC HOLD (VH Pin)
- 8.3.7 Adjustable Output Regulation Target (VOUT, TRK, VREF Pin)
- 8.3.8 Overvoltage Protection (VOUT Pin)
- 8.3.9 Power Good Indicator (PGOOD Pin)
- 8.3.10 Dynamically Programmable Switching Frequency (RT)
- 8.3.11 External Clock Synchronization (SYNC Pin)
- 8.3.12 Programmable Spread Spectrum (DITHER Pin)
- 8.3.13 Programmable Soft Start (SS Pin)
- 8.3.14 Wide Bandwidth Transconductance Error Amplifier and PWM (TRK, COMP Pin)
- 8.3.15 Current Sensing and Slope Compensation (CSP, CSN Pin)
- 8.3.16 Constant Peak Current Limit (CSP, CSN Pin)
- 8.3.17 Maximum Duty Cycle and Minimum Controllable On-Time Limits
- 8.3.18 Deep Sleep Mode and Bypass Operation (HO, CP Pin)
- 8.3.19 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LO, HO, HB Pin)
- 8.3.20 Thermal Shutdown Protection
- 8.4 Device Functional Modes
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
8.3.11 External Clock Synchronization (SYNC Pin)
The switching frequency of the device can be synchronized to an external clock by directly applying an external pulse signal to the SYNC pin. The internal clock is synchronized at the rising edge of the external synchronization pulse using an internal PLL. Connect the SYNC pin to ground if not used.
The external synchronization pulse must be greater than VSYNC in the high logic state and must be less than VSYNC in the low logic state. The duty cycle of the external synchronization pulse is not limited, but the minimum on-pulse and the minimum off-pulse widths must be greater than 100 ns. The frequency of the external synchronization pulse must satisfy the following two inequalities.
For example, an RT resistor is required for typical 350-kHz switching to cover from 263-kHz to 525-kHz clock synchronization without changing the RT resistor.
Figure 8-9 External Clock SynchronizationDrive the SYNC pin through a minimum 1-kΩ resistor if the BIAS pin voltage is less than the SYNC pin voltage in any conditions.