ZHCSMW2B December 2021 – December 2022 LM5123-Q1
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 說明（續(xù)）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Device Enable/Disable (EN, VH Pin)
- 8.3.2 High Voltage VCC Regulator (BIAS, VCC Pin)
- 8.3.3 Light Load Switching Mode Selection (MODE Pin)
- 8.3.4 VOUT Range Selection (RANGE Pin)
- 8.3.5 Line Undervoltage Lockout (UVLO Pin)
- 8.3.6 Fast Restart using VCC HOLD (VH Pin)
- 8.3.7 Adjustable Output Regulation Target (VOUT, TRK, VREF Pin)
- 8.3.8 Overvoltage Protection (VOUT Pin)
- 8.3.9 Power Good Indicator (PGOOD Pin)
- 8.3.10 Dynamically Programmable Switching Frequency (RT)
- 8.3.11 External Clock Synchronization (SYNC Pin)
- 8.3.12 Programmable Spread Spectrum (DITHER Pin)
- 8.3.13 Programmable Soft Start (SS Pin)
- 8.3.14 Wide Bandwidth Transconductance Error Amplifier and PWM (TRK, COMP Pin)
- 8.3.15 Current Sensing and Slope Compensation (CSP, CSN Pin)
- 8.3.16 Constant Peak Current Limit (CSP, CSN Pin)
- 8.3.17 Maximum Duty Cycle and Minimum Controllable On-Time Limits
- 8.3.18 Deep Sleep Mode and Bypass Operation (HO, CP Pin)
- 8.3.19 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LO, HO, HB Pin)
- 8.3.20 Thermal Shutdown Protection
- 8.4 Device Functional Modes
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGR|20
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購(gòu)信息
8.3.12 Programmable Spread Spectrum (DITHER Pin)
The device provides an optional programmable spread spectrum (clock dithering) function that is activated by connecting a capacitor between DITHER and AGND. A triangular waveform centered at 1.0 V is generated across the dither capacitor. This triangular waveform modulates the oscillator frequency by –6% to +5% of the frequency set by the RT resistor. The dither capacitance value sets the rate of the low frequency modulation.
Figure 8-10 Switching Frequency
DitheringFor the dithering circuit to effectively reduce peak EMI, the modulation frequency must be much less than the RT switching frequency. The dither capacitance which is required for a given modulation frequency (fMOD), can be calculated from Equation 9. Setting the fMOD to 9 kHz or 10 kHz is a good starting point.
Connecting DITHER to AGND deactivates clock dithering, and the internal oscillator operates at a fixed frequency set by the RT resistor. Clock dithering is also disabled when an external synchronization pulse is applied.
Figure 8-11 Dynamic Dither On/Off
Example