ZHCSLR1B December 2021 – December 2021 LDC3114-Q1
PRODUCTION DATA
The LDC3114-Q1 cannot drive the I2C clock (SCL), that is the device does not support clock stretching. In the unlikely event where the SCL is stuck LOW, power cycle any device that is holding the SCL to activate its internal Power-On Reset (POR) circuit. If the LDC is connected to the same power supply as that device, there will be about 66-ms setup time before the LDC becomes active again. For more information, refer to Section 8.1.4. If the data line (SDA) is stuck LOW, the I2C controller should send nine clock pulses. The device that is holding the bus LOW should release the bus sometime within those nine clocks. If not, then power cycle to clear the bus.
The LDC3114-Q1 has built-in monitors to check that the device is currently working. In the unlikely event of a device fault, the device state will be reset internally, and all the registers will be reset with default settings. For system robustness, TI recommends to check the value of a modified register periodically to monitor the device status and reload the register settings, if needed.