INTB, the LDC3114-Q1 interrupt pin, is asserted when a button press or an error condition occurs. The default polarity is active low and can be configured through Register INTPOL (Address 0x11).

Figure 8-13 shows the LDC3114-Q1 response to a single button press on Channel 0. At the end of the button sampling window following a press of Button 0, the OUT0 pin and INTB pin are asserted. The OUT_STATUS bit changes from 0 to 1, and remains so until a read of the STATUS register clears it. The OUTn (n = 0, 1, 2, or 3) and INTB pins are asserted until the end of the button sampling window following the release of the button.

Figure 8-13 Timing Diagram of a Single Button Press

Figure 8-14 shows the LDC3114-Q1 response to multiple button presses. In this example, after Button 0 is pressed, the OUT0 pin is asserted. After that, Button 1 is also pressed, following which Button 0 is released. The OUT0 pin is de-asserted and OUT1 pin asserted at the end of the next button sampling window. The INTB pin remains continuously asserted as long as at least one of the buttons is pressed. The OUT_STATUS bit only changes from 0 to 1 after the first button assertion.

Figure 8-14 Timing Diagram of Multiple Button Presses

The INTB pin also reports any error event. If an error occurs, the INTB pin is asserted and the error is reported in the STATUS register (Address 0x00). Refer to the Section 7.5 section for possible error events.

For Raw data access mode, the OUTx pins are not used and INTB pin along with error is also used to assert when the sampling cycle is complete and data is available for all channels.