ZHCSLR1B December 2021 – December 2021 LDC3114-Q1
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5 Register Maps
-
8 Application and Implementation
- 8.1
Application Information
- 8.1.1 Theory of Operation
- 8.1.2 Designing Sensor Parameters
- 8.1.3 Setting COM Pin Capacitor
- 8.1.4 Defining Power-On Timing
- 8.1.5 Configuring Button or Raw Data Scan Rate
- 8.1.6 Programming Button or Raw Data Sampling Window
- 8.1.7 Scaling Frequency Counter Output
- 8.1.8 Setting Button Triggering Threshold
- 8.1.9 Tracking Baseline
- 8.1.10 Mitigating False Button Detections
- 8.1.11 Reporting Interrupts for Button Presses, Raw Data Ready and Error Conditions
- 8.1.12 Estimating Supply Current
- 8.2 Typical Application
- 8.1
Application Information
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
8.1.4 Defining Power-On Timing
The low power architecture of the LDC3114-Q1 makes it possible for the device to be active all the time. When not being used, the LDC3114-Q1 can operate in Low Power Mode with a single standby power button, which typically consumes less than 10 μA. If additional power-saving is desired, or in the rare event where a power-on reset becomes necessary (see Section 7.3.8), the output data will become ready after 50-ms start-up time, about 1-ms optional register loading time, and two sampling windows for all active channels. Figure 8-5 shows the power-on timing of the LDC3114-Q1.
Figure 8-5 Power-On Timing