7.3.1 Multi-Channel and Single-Channel Operation

The LDC2112 provides two independent sensing channels; the LDC2114 provides four independent sensing channels. In the following sections, some parameters, such as DATAn and SENSORn_CONFIG, contain a channel index n. In those instances, n = 0 or 1 for LDC2112, and n = 0, 1, 2, or 3 for LDC2114.

The LDC2112's two available channels are always enabled in Normal Power Mode. The LDC2112 sequentially samples both channels at the configured scan rate. Either channel can be independently enabled in Low Power Mode by setting the LPENn (n = 0 or 1) bit fields in Register EN (Address 0x0C).

Any of the LDC2114’s four available channels can be independently enabled by setting the ENn and LPENn (n = 0, 1, 2, or 3) bit fields in Register EN (Address 0x0C). The low-power-enable bit LPENn only takes effect if the corresponding ENn bit is also set. If only one channel is set active, the LDC2114 periodically samples the single active channel at the configured scan rate. When several channels are set active, the LDC2114 operates in multi-channel mode, and it sequentially samples the active channels at the configured scan rate. Each channel of the LDC2114 can be independently enabled in Low Power Mode and Normal Power Mode.

7.3.2 Button Output Interfaces

Button events may be reported by using two methods. The first method is to monitor the OUTn pins (n = 0, 1, 2, or 3), which are push-pull outputs and can be used as interrupts to a micro-controller. The polarities of these pins are programmable through Register OPOL_DPOL (Address 0x1C). Any button press or error condition is also reported by the push-pull interrupt pin, INTB. Its polarity is configurable through Register INTPOL (Address 0x11). Any assertion of INTB is cleared upon reading Register STATUS (Address 0x00). Each push-pull output must be assigned to a dedicated general-purpose input pin on the micro-controller to avoid potential current fights.

The second method is by use of the LDC2112/LDC2114’s I²C interface. The Register OUT (Address 0x01) contains the fields OUT0, OUT1, OUT2, and OUT3, which indicate when a button press has been detected. For more advanced button press measurements, the output DATAn registers (n = 0, 1, 2, or 3, Addresses 0x02 through 0x09), which are 12-bit two’s complements, can be retrieved for all active buttons, and processed on a micro-controller. A valid button push is represented by a positive value. The polarity is configurable in Register OPOL_DPOL (Address 0x1C). The DATAn values can be used to implement multi-level buttons, where the data value is correlated to the amount of force applied to the button.

7.3.3 Programmable Button Sensitivity

The GAINn registers (Addresses 0x0E, 0x10, 0x12, and 0x14) enable sensitivity enhancement of individual buttons to ensure consistent behavior of different mechanical structures. The sensitivity has a 64-level gain factor for a normalized gain between 1 and 232. Each gain step increases the gain by an average of 9%.

The gain required for an application is primarily determined by the mechanical rigidity of each individual button. The individual gain steps are listed in the Gain Table.

7.3.4 Baseline Tracking

The LDC2112/LDC2114 incorporates a baseline tracking algorithm to automatically compensate for any slow change in the sensor output caused by environmental variations, such as temperature drift. The baseline tracking is configured independently for Normal Power Mode and Low Power Mode. For more information, refer to Tracking Baseline.

7.3.5 Integrated Button Algorithms

The LDC2112/LDC2114 features several algorithms that can mitigate false button detections due to mechanical non-idealities. The algorithms look for correlated button responses, for example, similar or opposite responses between two neighboring buttons, to determine if there is any undesirable mechanical crosstalk. For more information, refer to Mitigating False Button Detections.

7.3.6 I²C Interface

The LDC2112/LDC2114 features an I²C Interface that can be used to program the internal registers and read channel data. Before reading the OUT (Address 0x01) or channel DATAn (n = 0, 1, 2 or 3, Addresses 0x02 through 0x05) registers, the user should always read Register STATUS (Address 0x00) first to lock the data. The LDC2112/LDC2114 supports burst mode with auto-incrementing register addresses.

For the write sequence, there is a special handshake process that has to take place to ensure data integrity. The sequence of register write is illustrated as follows:

• Set CONFIG_MODE (Register RESET, Address 0x0A) bit = 1 to start the register write session
• Poll for RDY_TO_WRITE (Register STATUS, Address 0x00) bit = 1
• I²C write to configure registers
• Set CONFIG_MODE (Register RESET, Address 0x0A) bit = 0 to terminate the register write session

After CONFIG_MODE is de-asserted, the new scan cycle will start in less than 1 ms. The waveform of the above process is shown in Figure 12.

Figure 12. Timing Diagram Representing the States of the CONFIG_MODE and RDY_TO_WRITE Bits for an I²C Write Handshake

7.3.6.2 I²C Interface Specifications

The maximum speed of the I²C interface is 400 kHz. This sequence uses the standard I²C 7-bit slave address followed by an 8-bit pointer to set the register address. For both write and read, the address pointer will auto-increment as long as the master acknowledges.

Figure 13. I²C Sequence of Writing a Single Register

Figure 14. I²C Sequence of Writing Consecutive Registers

Figure 15. I²C Sequence of Reading a Single Register

Figure 16. I²C Sequence of Reading Consecutive Registers

7.4.1 Normal Power Mode

When the LPWRB input pin is set to V_DD, all enabled channels operate in Normal Power Mode. Each channel can be enabled independently through Register EN (Address 0x0C). For the electrical specification of Normal Power Mode Scan Rate, refer to Electrical Characteristics.

7.4.2 Low Power Mode

When the LPWRB input pin is set to Ground, only the low-power-enabled channels are active. Each channel can be enabled independently to operate in Low Power Mode through Register EN (Address 0x0C). For a channel to operate in the Low Power Mode, both the LPENn and ENn bits (n is the channel index) must be set to 1. The Low Power Mode allows for energy-saving monitoring of button activity. In this mode, the device is in an inactive power-saving state for the majority of the time. Lower scan rates correspond to lower current consumption. In addition, the individual button sampling window should be set to the lowest effective setting (this is system dependent, but typically 0.8 to 1 ms). For the electrical specification of the configurable Low Power Mode Scan Rate, refer to Electrical Characteristics.

If a channel is operational in both Low Power Mode and Normal Power Mode, it is recommended to toggle the LPWRB pin only after the button associated with that channel is released.

7.4.3 Configuration Mode

Before configuring any register settings, the device must be put into the configuration mode first. Setting CONFIG_MODE = 1 through Register RESET (Address 0x0A) stops data conversion and holds the device in configuration mode. Any device configuration changes can then be made. The current consumption in this mode is typically 0.3 mA. After all changes have been written, set CONFIG_MODE = 0 for normal operation. Refer to I2C Interface for more information.

Table 1. Register List

7.5.1 Individual Register Listings

Fields indicated with ‘Reserved’ must be written only with indicated values. Improper device operation may occur otherwise. The R/W column indicates the Read-Write status of the corresponding field. An ‘R/W’ entry indicates read and write capability, an ‘R’ indicates read-only, and a ‘W’ indicates write-only.

Before reading the OUT (Address 0x01) or channel DATAn registers (n = 0, 1, 2, or 3, Addresses 0x02 through 0x09), the user should always read the STATUS register (Address 0x00) first to lock the data. The LDC2112/LDC2114 supports burst mode with auto-incrementing register addresses.