国产在热线精品视频,国产一级精品视频毛片乱,色噜噜狠狠色综无码久久合欧美

ZHCSHX3A December 2014 – March 2018 LDC1312 , LDC1314

PRODUCTION DATA.

封裝選項

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DNT|12
- MPDS488B

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

8.1.6 Clocking Architecture

Optimum LDC1312/LDC1314 performance requires a clean reference clock with a limited frequency range. The device provides digital dividers for the ƒ_CLK and the sensor inputs. The dividers provide flexibility in system design, so that the full range of sensor frequencies can be supported with available f_CLK. Each channel has a dedicated divider configuration. Higher reference frequencies provide a higher sample rate for a given resolution.

Figure 54 shows the clock dividers and multiplexers of the LDC.

LDC1312 LDC1314 ldc1312-clocking-snoscz0.gif

Figure 54. Clocking Diagram

(1) LDC1314 only

In Figure 54, the key clocks are ƒ_INx, ƒ_REFx, and ƒ_CLK. ƒ_CLK is selected from either the internal clock source or external clock source (CLKIN). The frequency measurement reference clock, ƒ_REF, is derived from the ƒ_CLK source.

The internal oscillator is highly stable across temperature and is suitable for most LDC1312/4 applications. Applications requiring matched performance across multiple LDC1312/4 devices and/or requiring higher long-term stability may need an external oscillator. Note that some internal functions, such as watchdog timers, always use ƒ_INT for timing.

The ƒ_INx clock is derived from sensor frequency for channel x, ƒ_SENSORx. ƒ_REFx and ƒ_INx must meet the requirements listed in Table 40, depending on whether ƒ_CLK (reference clock) is the internal or external clock.

Table 40. Clock Frequency Requirements

MODE⁽¹⁾	REFERENCE SOURCE	VALID ƒ_REFx RANGE	VALID ƒ_INx RANGE	SET FIN_DIVIDERx to	VALID SETTLECOUNTx SETTINGS	VALID RCOUNTx SETTINGS
Multi-Channel	Internal	ƒ_REFx≤ 55 MHz	< ƒ_REFx /4	≥ b0001 ⁽²⁾	> 3	> 8
Multi-Channel	External	ƒ_REFx ≤ 40 MHz
Single-Channel	Either external or internal	ƒ_REFx ≤ 35 MHz

(1) Channels 2 and 3 are only available for LDC1314

(2) If ƒ_SENSOR ≥ 8.75 MHz, then FIN_DIVIDERx must be ≥ 2

Table 41 shows the clock configuration registers. Each input channel has a dedicated configuration which can be set independently.

Table 41. Clock Configuration Registers

CHANNEL⁽¹⁾	CLOCK	REGISTER	FIELD	VALUE
All	ƒ_CLK = Reference Clock Source	CONFIG, addr 0x1A	REF_CLK_SRC [9]	b0 = internal oscillator is used as the reference clock b1 = external clock source is used as the reference clock
0	ƒ_REF0	CLOCK_DIVIDERS0, addr 0x14	FREF_DIVIDER0 [9:0]	ƒ_REF0 = ƒ_CLK / FREF_DIVIDER0
1	ƒ_REF1	CLOCK_DIVIDERS1, addr 0x15	FREF_DIVIDER1 [9:0]	ƒ_REF1 = ƒ_CLK / FREF_DIVIDER1
2	ƒ_REF2	CLOCK_DIVIDERS2, addr 0x16	FREF_DIVIDER2 [9:0]	ƒ_REF2 = ƒ_CLK / FREF_DIVIDER2
3	ƒ_REF3	CLOCK_DIVIDERS3, addr 0x17	FREF_DIVIDER3 [9:0]	ƒ_REF3 = ƒ_CLK / FREF_DIVIDER3
0	ƒ_IN0	CLOCK_DIVIDERS0, addr 0x14	FIN_DIVIDER0 [15:12]	ƒ_IN0 = ƒ_SENSOR0 / FIN_DIVIDER0
1	ƒ_IN1	CLOCK_DIVIDERS1, addr 0x15	FIN_DIVIDER1 [15:12]	ƒ_IN1 = ƒ_SENSOR1 / FIN_DIVIDER1
2	ƒ_IN2	CLOCK_DIVIDERS2, addr 0x16	FIN_DIVIDER2 [15:12]	ƒ_IN2 = ƒ_SENSOR2/ FIN_DIVIDER2
3	ƒ_IN3	CLOCK_DIVIDERS3, addr 0x17	FIN_DIVIDER3 [15:12]	ƒ_IN3 = ƒ_SENSOR3 / FIN_DIVIDER3

(1) Channels 2 and 3 are only available for LDC1314