ZHCSHX3A December 2014 – March 2018 LDC1312 , LDC1314
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6
Register Maps
- 7.6.1 Register List
- 7.6.2 Address 0x00, DATA0
- 7.6.3 Address 0x02, DATA1
- 7.6.4 Address 0x04, DATA2 (LDC1314 only)
- 7.6.5 Address 0x06, DATA3 (LDC1314 only)
- 7.6.6 Address 0x08, RCOUNT0
- 7.6.7 Address 0x09, RCOUNT1
- 7.6.8 Address 0x0A, RCOUNT2 (LDC1314 only)
- 7.6.9 Address 0x0B, RCOUNT3 (LDC1314 only)
- 7.6.10 Address 0x0C, OFFSET0
- 7.6.11 Address 0x0D, OFFSET1
- 7.6.12 Address 0x0E, OFFSET2 (LDC1314 only)
- 7.6.13 Address 0x0F, OFFSET3 (LDC1314 only)
- 7.6.14 Address 0x10, SETTLECOUNT0
- 7.6.15 Address 0x11, SETTLECOUNT1
- 7.6.16 Address 0x12, SETTLECOUNT2 (LDC1314 only)
- 7.6.17 Address 0x13, SETTLECOUNT3 (LDC1314 only)
- 7.6.18 Address 0x14, CLOCK_DIVIDERS0
- 7.6.19 Address 0x15, CLOCK_DIVIDERS1
- 7.6.20 Address 0x16, CLOCK_DIVIDERS2 (LDC1314 only)
- 7.6.21 Address 0x17, CLOCK_DIVIDERS3 (LDC1314 only)
- 7.6.22 Address 0x18, STATUS
- 7.6.23 Address 0x19, ERROR_CONFIG
- 7.6.24 Address 0x1A, CONFIG
- 7.6.25 Address 0x1B, MUX_CONFIG
- 7.6.26 Address 0x1C, RESET_DEV
- 7.6.27 Address 0x1E, DRIVE_CURRENT0
- 7.6.28 Address 0x1F, DRIVE_CURRENT1
- 7.6.29 Address 0x20, DRIVE_CURRENT2 (LDC1314 only)
- 7.6.30 Address 0x21, DRIVE_CURRENT3 (LDC1314 only)
- 7.6.31 Address 0x7E, MANUFACTURER_ID
- 7.6.32 Address 0x7F, DEVICE_ID
-
8 Application and Implementation
- 8.1
Application Information
- 8.1.1 Conductive Objects in a Time-Varying EM Field
- 8.1.2 L-C Resonators
- 8.1.3 Multi-Channel and Single Channel Operation
- 8.1.4 Sensor Conversion Time
- 8.1.5 Sensor Current Drive Configuration
- 8.1.6 Clocking Architecture
- 8.1.7 Input Deglitch Filter
- 8.1.8 Device Status Registers
- 8.1.9 Multi-Channel Data Readback
- 8.2 Typical Application
- 8.1
Application Information
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機(jī)械、封裝和可訂購信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DNT|12
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購信息
7.5.1 I2C Interface Specifications
The LDC1312/4 use I2C for register access with a maximum speed of 400 kbit/s. The device registers are 16 bits wide, and so a repeated start is used to access the 2nd byte of data. This sequence follows the standard I2C 7bit slave address followed by an 8 bit pointer register byte to set the register address. Refer to Figure 11 and Figure 12 for proper protocol diagrams. The device does not use I2C clock stretching.
When the ADDR pin is set low, the device I2C address is 0x2A; when the ADDR pin is set high, the I2C address is 0x2B. The ADDR pin setting can be changed while the device is in Shutdown Mode to select the alternate I2C address.
Figure 11. I2C Write Register Sequence
Figure 12. I2C Read Register Sequence