ZHCSKH7 November 2019 LDC1001
PRODUCTION DATA.
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| ƒSCLK | Serial clock frequency | 4 | MHz | |||
| tPH | SCLK pulse width high | ƒSCLK = 4 MHz | 0.4 / ƒSCLK | s | ||
| tPL | SCLK pulse width low | ƒSCLK = 4 MHz | 0.4 / ƒSCLK | s | ||
| tSU | SDI setup time | 10 | ns | |||
| tH | SDI hold time | 10 | ns | |||
| tODZ | SDO driven-to-tristate time | Measured at 10% / 90% point | 20 | ns | ||
| tOZD | SDO tristate-to-driven time | Measured at 10% / 90% point | 20 | ns | ||
| tOD | SDO output delay time | 20 | ns | |||
| tCSS | CSB setup time | 20 | ns | |||
| tCSH | CSB hold time | 20 | ns | |||
| tIAG | Inter-access gap | 100 | ns | |||
| tDRDYB | Data ready pulse width | Data ready pulse at every 1 / ODR if no data is read | 1 / ƒsensor | s | ||
Figure 1. Write Timing Diagram
Figure 2. Read Timing Diagram