ZHCSEN6D October 2014 – February 2022 DS90UH948-Q1
PRODUCTION DATA
In reverse channel SPI operation, the deserializer samples the Peripheral select (CS), SPI clock (SCLK) into the internal oscillator clock domain. Upon detection of the active SPI clock edge, the deserializer also samples the SPI data (PICO). The SPI data samples are stored in a buffer to be passed to the serializer over the back channel. The deserializer sends SPI information in a back channel frame to the serializer. In each back channel frame, the deserializer sends an indication of the CS value. The CS must be inactive (high) for at least one back-channel frame period to ensure propagation to the serializer.
Because data is delivered in separate back channel frames and buffered, the data may be regenerated in bursts. #SNLS4791070 shows an example of the SPI data regeneration when the data arrives in three back channel frames. The first frame delivered the CS active indication, the second frame delivered the first three data bits, and the third frame delivers the additional data bits.
For reverse channel SPI reads, the SPI Controller must wait for a round-trip response before generating the sampling edge of the SPI clock. This is similar to operation in forward channel mode. Note that at most one data/clock sample is sent per back channel frame.
For both reverse-channel SPI writes and reads, the SPI_CS signal must be deasserted for at least one back-channel frame period.
| BACK CHANNEL FREQUENCY | DEASSERTION REQUIREMENT |
|---|---|
| 5 Mbps | 7.5 μs |
| 10 Mbps | 3.75 μs |
| 20 Mbps | 1.875 μs |