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ZHCSEN6D October 2014 – February 2022 DS90UH948-Q1

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

NKD|64
- MPQS032C

散熱焊盤機械數據 (封裝 | 引腳)

NKD|64
- QFND765

訂購信息

6.5 DC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER		TEST CONDITIONS	PIN/FREQ.	MIN	TYP	MAX	UNIT
POWER CONSUMPTION
P_T	Total power consumption, normal operation	PCLK = 170 MHz. 2-lane FPD-Link III input, dual-link OLDI output	VDD		858	1146	mW
P_Z	Total power consumption, power-down mode	PDB = 0 V	VDD		40	70	mW
SUPPLY CURRENT
IDD12	Supply current, normal operation	PCLK = 170 MHz. 2-lane FPD-Link III input, dual-link OLDI output	VDD12 = 1.2 V		169	223	mA
IDD33			VDD33 = 3.6 V		168	222	mA
IDDIO			VDDIO = 1.89 V or 3.6 V		14	19	mA
IDD12	Supply current, normal operation	PCLK = 192 MHz 2-lane FPD-Link III input, dual link OLDI Output	VDD12 = 1.2 V		189		mA
IDD12			VDD33 = 3.6 V		188		mA
IDD33			VDD33 = 3.6 V		188		mA
IDDIO			VDDIO = 1.89 V or 3.6 V		16		mA
IDD12Z	Supply current, power-down mode	PDB = 0 V	VDD12 = 1.2 V		2	30	mA
IDD33Z			VDD33 = 3.6 V		2	8	mA
IDDIOZ			VDDIO = 1.89 V or 3.6 V		0.1	1	mA
3.3-V LVCMOS I/O (V_(VDDIO) = 3.3 V ± 10%)
V_IH	High level input voltage		PDB, BISTEN	2		V_(VDDIO)	V
V_IL	Low level input voltage		PDB, BISTEN	0		0.8	V
V_IH	High level input voltage		BISTC, GPIO[3:0], D_GPIO[3:0], I2S_DA, I2S_DB, I2S_DC, I2S_DD, I2S_CLK, I2S_WC, LOCK, PASS	2		V_(VDDIO)	V
V_IL	Low level input voltage			0		0.8	V
I_IN	Input current	V_IN = 0 V or V_(VDDIO)		–10		10	μA
I_IN-STRAP	Strap pin input current	V_IN = 0V or V_(VDD33)	IDX, MODE_SEL0, MODE_SEL1	-1		1	μA
V_OH	High level output voltage	I_OH = –4 mA	BISTC, GPIO[3:0], D_GPIO[3:0], I2S_DA, I2S_DB, I2S_DC, I2S_DD, I2S_CLK, I2S_WC, LOCK, PASS	2.4		V_(VDDIO)	V
V_OL	Low level output voltage	I_OL = 4 mA		0		0.4	V
I_OS	Output short-circuit current	V_OUT = 0 V			–55		mA
I_OZ	Tri-state output current	PDB = 0 V V_OUT = 0 V or V_(VDDIO)		–20		20	μA
C_IN	Input capacitance					10	pF
1.8-V LVCMOS I/O (V_(VDDIO) = 1.8 V ± 5%)
V_IH	High level input voltage		PDB, BISTEN	1.5		V_(VDDIO)	V
V_IL	High level input voltage		PDB, BISTEN	0		0.35 × V_(VDDIO)	V
V_IH	High level input voltage		BISTC, GPIO[3:0], D_GPIO[3:0], I2S_DA, I2S_DB, I2S_DC, I2S_DD, I2S_CLK, I2S_WC, LOCK, PASS	0.65 × V_(VDDIO)		V_(VDDIO)	V
V_IL	Low level input voltage			0		0.35 × V_(VDDIO)	V
I_IN	Input current	V_IN = 0V or V_(VDDIO)		–10		10	μA
V_OH	High level output voltage	I_OH = –4 mA		V_(VDDIO) – 0.45		V_(VDDIO)	V
V_OL	Low level output voltage	I_OL = 4 mA		0		0.45	V
I_OS	Output short-circuit current	V_OUT = 0 V			–35		mA
I_OZ	Tri-state output current	PDB = 0 V V_OUT = 0 V or V_(VDDIO)		–20		20	μA
C_IN	Input capacitance					10	pF
SERIAL CONTROL BUS (V_(VDDIO) = 1.8 V ± 5% OR 3.3V ±10%)
V_IH	Input high level	V_(VDDIO) = 3.0 V to 3.6 V	I2C_SDA, I2C_SCL	2		V_(VDDIO)	V
V_IL	Input low level	V_(VDDIO) = 3.0 V to 3.6 V		0		0.9	V
V_IH	Input high level	V_(VDDIO) = 1.71 V to 1.89 V		1.58		V_(VDDIO)	V
V_IL	Input low level	V_(VDDIO) = 1.71 V to 1.89 V		GND		0.9	V
V_HYS	Input hysteresis				50		mV
V_OL	Output low level	I_OL = 4 mA		0		0.4	V
I_IN	Input current	V_IN = 0 V or V_(VDDIO)		–10		10	μA
FPD-LINK III INPUT
V_TH	Differential threshold high voltage	V_CM = 2.1 V	RIN0+, RIN0– RIN1+, RIN1–			50	mV
V_TL	Differential threshold low voltage			–50			mV
V_ID	Input differential threshold			100			mV
V_CM	Differential common-mode voltage				2.1		V
R_T	Internal termination resistor - differential			80	100	120	Ω
LVDS DRIVER
V_OD	Output voltage swing (differential)	R_L =100 Ω, VOD Setting 1. See GUID-07D6C494-EEE9-4B64-8C23-0372B8F8A506.html#SNLS4407184. See GUID-60BE0D45-4ECE-419B-8DBC-A833CCA113EF.html#GUID-60BE0D45-4ECE-419B-8DBC-A833CCA113EF Register 0x4B for configuration details.	D0±, D1±, D2±, D3±, D4±, D5±, D6±, D7±, CLK1±, CLK2±	220	380	540	mV_P-P
		R_L =100 Ω, VOD Setting 2. See GUID-07D6C494-EEE9-4B64-8C23-0372B8F8A506.html#SNLS4407184. See GUID-60BE0D45-4ECE-419B-8DBC-A833CCA113EF.html#GUID-60BE0D45-4ECE-419B-8DBC-A833CCA113EF Register 0x4B for configuration details.		370	550	730	mV_P-P
		R_L = 100 Ω, VOD Setting 3. See GUID-07D6C494-EEE9-4B64-8C23-0372B8F8A506.html#SNLS4407184. See GUID-60BE0D45-4ECE-419B-8DBC-A833CCA113EF.html#GUID-60BE0D45-4ECE-419B-8DBC-A833CCA113EF Register 0x4B for configuration details.		460	650	840	mV_P-P
		R_L = 100 Ω, VOD Setting 4. See GUID-07D6C494-EEE9-4B64-8C23-0372B8F8A506.html#SNLS4407184. See GUID-60BE0D45-4ECE-419B-8DBC-A833CCA113EF.html#GUID-60BE0D45-4ECE-419B-8DBC-A833CCA113EF Register 0x4B for configuration details.		530	750	970	mV_P-P
ΔV_OD	Change in V_OD between complementary output states	R_L = 100 Ω			1	50	mV
V_OS	Offset voltage	R_L = 100 Ω. See GUID-07D6C494-EEE9-4B64-8C23-0372B8F8A506.html#SNLS4407184.		1.125	1.2	1.375	V
ΔV_OS	Change in V_OS between complementary Output States	R_L = 100 Ω			1	50	mV
I_OS	Output short-circuit current				-20		mA
I_OZ	Output tri-state LVDS driver current	PDB = 0 V		–500		500	μA
LOOP-THROUGH MONITOR OUTPUT
V_OD	Differential output voltage	R_L = 100 Ω	CMLOUTP, CMLOUTN		360		mV