ZHCSEN6D October 2014 – February 2022 DS90UH948-Q1
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 DC Electrical Characteristics
- 6.6 AC Electrical Characteristics
- 6.7 Timing Requirements for the Serial Control Bus
- 6.8 Switching Characteristics
- 6.9 Timing Diagrams and Test Circuits
- 6.10 Typical Characteristics
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 High-Speed Forward Channel Data Transfer
- 7.3.2 Low-Speed Back Channel Data Transfer
- 7.3.3 FPD-Link III Port Register Access
- 7.3.4 Oscillator Output
- 7.3.5 Clock and Output Status
- 7.3.6 LVCMOS VDDIO Option
- 7.3.7 Power Down (PDB)
- 7.3.8 Interrupt Pin — Functional Description and Usage (INTB_IN)
- 7.3.9 General-Purpose I/O (GPIO)
- 7.3.10 SPI Communication
- 7.3.11 Backward Compatibility
- 7.3.12 Adaptive Equalizer
- 7.3.13 I2S Audio Interface
- 7.3.14 HDCP Repeater
- 7.3.15 Built-In Self Test (BIST)
- 7.3.16 Internal Pattern Generation
- 7.4
Device Functional Modes
- 7.4.1
Configuration Select MODE_SEL[1:0]
- 7.4.1.1 1-Lane FPD-Link III Input, Single Link OpenLDI Output
- 7.4.1.2 1-Lane FPD-Link III Input, Dual Link OpenLDI Output
- 7.4.1.3 2-Lane FPD-Link III Input, Dual Link OpenLDI Output
- 7.4.1.4 2-Lane FPD-Link III Input, Single Link OpenLDI Output
- 7.4.1.5 1-Lane FPD-Link III Input, Single Link OpenLDI Output (Replicate)
- 7.4.2 MODE_SEL[1:0]
- 7.4.3 OpenLDI Output Frame and Color Bit Mapping Select
- 7.4.1
Configuration Select MODE_SEL[1:0]
- 7.5 Image Enhancement Features
- 7.6
Programming
- 7.6.1 Serial Control Bus
- 7.6.2 Multi-Controller Arbitration Support
- 7.6.3 I2C Restrictions on Multi-Controller Operation
- 7.6.4 Multi-Controller Access to Device Registers for Newer FPD-Link III Devices
- 7.6.5 Multi-Controller Access to Device Registers for Older FPD-Link III Devices
- 7.6.6 Restrictions on Control Channel Direction for Multi-Controller Operation
- 7.7 Register Maps
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- NKD|64
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- NKD|64
訂購(gòu)信息
8.2.1 Design Requirements
For the typical design application, use the following as input parameters.
| DESIGN PARAMETER | EXAMPLE VALUE |
|---|---|
| VDD33 | 3.3 V |
| VDDIO | 1.8 or 3.3 V |
| VDD12 | 1.2 V |
| AC-coupling capacitor for STP with 925/927: RIN[1:0]± | 100 nF |
| AC-coupling capacitor for STP with 929/947/949: RIN[1:0]± | 33 nF - 100 nF |
| AC-coupling capacitor for Coax with 921: RIN[1:0]+ | 100 nF |
| AC-coupling capacitor for Coax with 921: RIN[1:0]- | 47 nF |
| AC-coupling capacitor for Coax with 929/947/949: RIN[1:0]+ | 33 nF - 100 nF |
| AC-coupling capacitor for Coax with 929/947/949: RIN[1:0]+ | 15 nF - 47 nF |
The SER/DES supports only AC-coupled interconnects through an integrated DC-balanced decoding scheme. External AC-coupling capacitors must be placed in series in the FPD-Link III signal path as shown in #SNLS4791056. For applications using single-ended 50-Ω coaxial cable, the unused data pins (RIN0– and RIN1–) must use a 15-nF to 47-nF capacitor and must be terminated with a 50-Ω resistor.
Figure 8-4 AC-Coupled Connection (STP)
Figure 8-5 AC-Coupled Connection (Coaxial)For high-speed FPD–Link III transmissions, use the smallest available package for the AC-coupling capacitor. This minimizes degradation of signal quality due to package parasitics.