ZHCSMR4A november 2020 – november 2020 DS90UB662-Q1
PRODUCTION DATA
The SCL Low Time register field configures the low pulse width of the SCL output when the serializer is the master on the local I2C bus. This value is also used as the SDA setup time by the I2C Slave for providing data prior to releasing SCL during accesses over the Bidirectional control channel. Units are 40 ns for the nominal oscillator clock frequency. The default value is set to approximately 100 kHz with the internal oscillator clock running at nominal 25 MHz. Delay includes 4 additional oscillator clock periods. The internal oscillator has ±10% variation when REFCLK is not applied, which must be taken into account when setting the SCL High and Low Time registers.
| BIT | FIELD | TYPE | DEFAULT | DESCRIPTION |
|---|---|---|---|---|
| 7:0 | SCL_LOW_TIME | R/W | 0x7A | I2C SCL Low Time This field configures the low pulse width of the SCL output when the Serializer is the Master on the local I2C bus. This value is also used as the SDA setup time by the I2C Slave for providing data prior to releasing SCL during accesses over the Bi-directional Control Channel. Units are 40 ns for the nominal oscillator clock frequency. The default value is set to provide a minimum 5us SCL low time with the reference clock at 25 MHz + 100ppm. The delay includes 5 additional clock periods. Min_delay = 39.996ns * (SCL_LOW_TIME+ 5) |