ZHCSMR4A november 2020 – november 2020 DS90UB662-Q1
PRODUCTION DATA
CSI-2 TX port-specific register. The CSI-2 Port Select register 0x32 configures which unique CSI-2 TX port registers can be accessed by I2C read and write commands.
| BIT | FIELD | TYPE | DEFAULT | DESCRIPTION |
|---|---|---|---|---|
| 7:5 | RESERVED | - | 0x0 | Reserved |
| 4 | IS_RX_PORT_INT | R/RC | 0 | RX Port Interrupt A Receiver port interrupt has been generated for one of the RX Ports being forwarded to the CSI-2 Transmit Port. A read of the associated port receive status registers will clear this interrupt. See the PORT_ISR_HI and PORT_ISR_LO registers for details. |
| 3 | IS_CSI_SYNC_ERROR | R/RC | 0 | CSI-2 Sync Error interrupt A synchronization error has been detected for multiple video stream inputs to the CSI-2 Transmitter. |
| 2 | IS_CSI_SYNC | R/RC | 0 | CSI-2 Synchronized interrupt CSI-2 Transmit Port assertion of CSI-2 Synchronized Status. Current status for CSI-2 Sync can be read from the TX_PORT_SYNC flag in the CSI_STS register. |
| 1 | IS_CSI_PASS_ERROR | R/RC | 0 | CSI-2 RX Pass Error interrupt A deassertion of CSI-2 Pass has been detected on one of the RX Ports being forwarded to the CSI-2 Transmit Port |
| 0 | IS_CSI_PASS | R/RC | 0 | CSI-2 Pass interrupt CSI-2 Transmit Port assertion of CSI-2 Pass detected. Current status for the CSI-2 Pass indication can be read from the TX_PORT_PASS flag in the CSI_STS register |