ZHCSMR4A november 2020 – november 2020 DS90UB662-Q1
PRODUCTION DATA
RX port-specific register. The FPD-Link III Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.
| BIT | FIELD | TYPE | DEFAULT | DESCRIPTION |
|---|---|---|---|---|
| 7:3 | RESERVED | - | 0x0 | Reserved |
| 2 | IE_FPD3_ENC_ERR | R/W | 0 | Interrupt on FPD-Link III Receiver Encoding Error When enabled, an interrupt is generated on detection of an encoding error on the FPD-Link III interface for the receive port as reported in the FPD3_ENC_ERROR bit in the RX_PORT_STS2 register |
| 1 | IE_BCC_SEQ_ERR | R/W | 0 | Interrupt on BCC SEQ Sequence Error When enabled, an interrupt is generated if a Sequence Error is detected for the Bi-directional Control Channel forward channel receiver as reported in the BCC_SEQ_ERROR bit in the RX_PORT_STS1 register. |
| 0 | IE_BCC_CRC_ERR | R/W | 0 | Interrupt on BCC CRC error detect When enabled, an interrupt is generated if a CRC error is detected on a Bi-directional Control Channel frame received over the FPD-Link III forward channel as reported in the BCC_CRC_ERROR bit in the RX_PORT_STS1 register. |