ZHCSMR4A november 2020 – november 2020 DS90UB662-Q1
PRODUCTION DATA
| BIT | FIELD | TYPE | DEFAULT | DESCRIPTION |
|---|---|---|---|---|
| 7 | INT | R | 0 | Global Interrupt: Set if any enabled interrupt is indicated in the individual status bits in this register. The setting of this bit is not dependent on the INT_EN bit in the INTERRUPT_CTL register but does depend on the IE_xxx bits. For example, if IE_RX0 and IS_RX0 are both asserted, the INT bit is set to 1. |
| 6 | RESERVED | - | 0 | Reserved |
| 5 | Reserved | R | 0 | Reserved |
| 4 | IS_CSI_TX | R | 0 | CSI-2 Transmit Port Interrupt: An interrupt has occurred for CSI-2 Transmitter Port. This interrupt is cleared upon reading the CSI_TX_ISR register for CSI-2 Transmit Port. |
| 3 | IS_RX3 | R | 0 | RX Port 3 Interrupt: This interrupt is cleared by reading the associated status register(s) for the event(s) that caused the interrupt. The status registers are RX_PORT_STS1, RX_PORT_STS2, and CSI_RX_STS. |
| 2 | IS_RX2 | R | 0 | RX Port 2 Interrupt: An interrupt has occurred for Receive Port 2. This interrupt is cleared by reading the associated status register(s) for the event(s) that caused the interrupt. The status registers are RX_PORT_STS1, RX_PORT_STS2, and CSI_RX_STS. |
| 1 | IS_RX1 | R | 0 | RX Port 1 Interrupt: 0x An interrupt has occurred for Receive Port 1. This interrupt is cleared by reading the associated status register(s) for the event(s) that caused the interrupt. The status registers are RX_PORT_STS1, RX_PORT_STS2, and CSI_RX_STS. |
| 0 | IS_RX0 | R | 0 | RX Port 0 Interrupt: An interrupt has occurred for Receive Port 0. This interrupt is cleared by reading the associated status register(s) for the event(s) that caused the interrupt. The status registers are RX_PORT_STS1, RX_PORT_STS2, and CSI_RX_STS. |