ZHCSOU0 February 2023 DS90UB635-Q1
PRODUCTION DATA
The DS90UB635-Q1 supports several clocking schemes, which are selected through the MODE pin. In the DS90UB635-Q1, the forward channel operates at a higher bandwidth than the requirement set by the video data transported, and the forward channel data rate is set by a reference clock. The clocking mode determines what the device uses as the reference clock, and the most common configuration is synchronous mode in which no local reference oscillator is required. See #GUID-85503A34-F236-423D-A62C-8964FB944685/T4587943-20 for more information.
The default mode of the DS90UB635-Q1 is set by the application of a bias on the MODE pin during power up. More information on setting the operation modes can be found in GUID-D3FB3F17-0D46-46BE-B453-C43BF4089914.html#GUID-D3FB3F17-0D46-46BE-B453-C43BF4089914.
| MODE | DIVIDE | REFERENCE SOURCE | REF FREQUENCY (MHz) | FC DATA RATE | CSI BANDWIDTH ≤(4) | CLK_OUT (3) |
|---|---|---|---|---|---|---|
| Synchronous | N/A | Back Channel(1) | 23 - 26 | f × 160 | f × 128 | f × 160 / HS_CLK_DIV × (M/N) |
| Synchronous (Half-rate) | N/A | Back Channel(1) | 11.5 - 13 | f × 160 | f × 128 | f × 160 / HS_CLK_DIV × (M/N) |
| Non-Synchronous external clock | CLKIN_DIV = 1, | External Clock(2) | 25 - 52 | f × 80 | f × 64 | f × 80 / HS_CLK_DIV × (M/N) |
| CLKIN_DIV = 2, | External clock (2) | 50 - 104 | f × 40 | f × 32 | f × 40 / HS_CLK_DIV × (M/N) | |
| Non-Synchronous Internal Clock | CLKIN_DIV = 1, OSCCLK_SEL = 1 | 635 Internal Clock | 48.4 - 51 | f × 80 | f × 64 | N/A |
| Non-Synchronous Internal Clock (Half-rate) | OSCCLK_SEL = 0 | 635 Internal Clock | 24.2 - 25.5 | f × 80 | f × 64 | N/A |
| DVP External Clock Deserializer Mode: RAW10 | N/A | External clock | 25 - 66.5 | f × 28 | f × 20 | f × 28 / HS_CLK_DIV × (M/N) |
| DVP External Clock Deserializer Mode: RAW12 HF | N/A | External clock | 25 - 70 | f × 28 | f × 18 | f × 28 / HS_CLK_DIV × (M/N) |