ZHCSOU0 February 2023 DS90UB635-Q1
PRODUCTION DATA
The DS90UB635-Q1 serializer can be placed into DVP mode to be backward-compatible with the DS90UB6xx-Q1 deserializer in DVP Backwards Compatibility Mode. While the mode should have been configured using the Mode pin on the DS90UB635-Q1 serializer, the register MODE_SEL register 0x03[2:0] can be used to verify or override the current mode. This field always indicates the mode setting of the device. When bit 4 of this register is 0, this field is read-only and shows the mode setting. Mode is latched from strap value when PDB transitions LOW to HIGH, and the value should read back 101 (0x5) if the resistive strap is set correctly to DVP external clock backward-compatible mode. Alternatively, when bit 4 of this register is set to 1, the MODE field is read/write and can be programmed to 101 to assign the correct backward-compatible MODE. This is shown in Table 7-16.
CSI-2 input data provided to the DS90UB635-Q1 serializer must be synchronized to the input frequency applied to CLKIN when using DVP external clock mode. The PCLK frequency output from the DS90UB6xx-Q1 deserializer will also be related to CLKIN when in DVP external clock mode. See Backward compatibility modes for operation with parallel output deserializers (SNLA270) for more information.
| REGISTER | REGISTER NAME | REGISTER DESCRIPTION |
|---|---|---|
| 0X03 | MODE_SEL | Used to override and verify strapped value, if necessary, and to configure for DVP with an external clock. |
| 0X04 | BC_MODE_SELECT | Allows DVP mode overwrites to RAW 10 or RAW 12. |
| 0X10 | DVP_CFG | Allows configuration of data in DVP mode. This includes data types like long, YUV, and specified types. |
| 0X11 | DVP_DT | Allows packets with certain data type regardless of RAW 10 or 12 mode if DVP_DT_MATCH_EN is asserted. |