ZHCSOU0 February 2023 DS90UB635-Q1
PRODUCTION DATA
The DS90UB635-Q1 provides an option for a programmable reference output clock to meet the system clock input requirements of various sensors. The control of the clock output frequency is set by the input divider and M value in register 0x06 and the N value in register 0x07.
| BIT | FIELD | TYPE | DEFAULT | DESCRIPTION |
|---|---|---|---|---|
| 7:5 | HS_CLK_DIV | R/W | 0x2 | Clock source of M/N divider is based on the forward channel data rate divided by this register field. 000: Div by 1 001: Div by 2 010: Div by 4 011: Div by 8 100: Div by 16 |
| 4:0 | DIV_M_VAL | R/W | 0x01 | M value for M/N divider for CLKOUT. CLKOUT can be programmed using the M/N ratio of an internal high-speed clock to generate a clock output based on the system sensor requirement. When selecting the M/N ratio, they should be set to yield the CLKOUT frequency less than 100 MHz. The M value should be ≥ 0. Setting M to 0 will disable CLKOUT and output will remain static high or low. |