ZHCSOU0 February 2023 DS90UB635-Q1
PRODUCTION DATA
The proxy controller timing parameters are based on the internal reference clock. The I2C controller regenerates the I2C read or write access using timing controls in registers 0x0B and 0x0C to regenerate the clock and data signals to meet the desired I2C timing in standard, fast, or fast-plus modes of operation.
I2C controller SCL high time is set in register 0x0B. This field configures the high pulse width of the SCL output when the serializer is the controller on the local I2C bus. The default value is set to provide a minimum 5-μs SCL high time with the internal reference clock at 26.25 MHz including five additional oscillator clock periods or synchronization and response time. Units are 38.1 ns for the nominal oscillator clock frequency, giving Min_delay = 38.1 ns × (SCL_HIGH_TIME + 5).
I2C controller SCL low time is set in register 0x0C. This field configures the low pulse width of the SCL output when the serializer is the controller on the local deserializer I2C bus. This value is also used as the SDA setup time by the I2C target for providing data prior to releasing SCL during accesses over the bidirectional control channel. The default value is set to provide a minimum 5-μs SCL high time with the reference clock at 26.25 MHz including five additional oscillator clock periods or synchronization and response time. Units are 38.1 ns for the nominal oscillator clock frequency, giving Min_delay = 38.1 ns × (SCL_HIGH_TIME + 5). See #GUID-6FD51115-502A-441C-ACD5-387DE6888B85/T4585536-29 example settings for standard mode, fast mode, and fast mode plus timing.
| I2C MODE | SCL HIGH TIME | SCL LOW TIME | ||
|---|---|---|---|---|
| 0x0B | NOMINAL DELAY | 0x0C | NOMINAL DELAY | |
| Standard | 0x7F | 5.03 μs | 0x7F | 5.03 μs |
| Fast | 0x13 | 0.914 μs | 0x26 | 1.64 μs |
| Fast - Plus | 0x06 | 0.419 μs | 0x0B | 0.648 μs |