ZHCSOU0 February 2023 DS90UB635-Q1
PRODUCTION DATA
The DS90UB635 can operate in one of many different modes. The default mode is selected by the bias voltage applied to the MODE pin during power-up. To set this voltage, a potential divider between VDD and GND is used to apply the appropriate bias After Power up, the MODE can be read, or changed through register access.
| MODE SELECT | VTARGET VOLTAGE RANGE | VTARGET STRAP VOLTAGE | SUGGESTED STRAP RESISTORS (1% TOL) | DESCRIPTION | ||||
|---|---|---|---|---|---|---|---|---|
| MODE | NAME | RATIO MIN | RATIO TYP | RATIO MAX | V(VDD) = 1.8 V | RHIGH (k? ) | RLOW (k? ) | |
| 0 | Synchronous | 0 | 0 | 0.133 x V(VDD) | 0 | OPEN | 10 | CSI-2 Synchronous mode – FPD-Link III Clock reference derived from the deserializer. |
| 2 | Non-Synchronous External Clock | 0.288 x V(VDD) | 0.325 x V(VDD) | 0.367 x V(VDD) | 0.586 | 75 | 35.7 | CSI-2 Non-synchronous clock – FPD-Link III Clock reference derived from external clock reference input on CLKIN pin. |
| 3 | Non-Synchronous Internal Clock | 0.412 x V(VDD) | 0.443 x V(VDD) | 0.474 x V(VDD) | 0.792 | 71.5 | 56.2 | CSI-2 Non-synchronous – FPD-Link III Clock reference derived from internal AON clock. |
| 5 (1) | DVP Mode | 0.642 x V(VDD) | 0.673 x V(VDD) | 0.704 x V(VDD) | 1.202 | 39.2 | 78.7 | DVP with External clock. |